Inventor · disambiguated record
Andy Wei
Also filed as: WEI ANDY · WEI ANDY C · WEI ANDY CHIH-HUNG
218 granted patents·58 pending applications·1,895 citations·filing 2002–2024
99Inventor score
Top patents by PatentIndex Score
276 records- 0198US9368395B1Self-aligned via and air gapGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 14, 2016·39 cites·16 claims
- 0298US9362165B12D self-aligned via first process flowGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·49 cites·15 claims
- 0398US8846491B1Forming a diffusion break during a RMG processGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 30, 2014·97 cites·20 claims
- 0498US8753940B1Methods of forming isolation structures and fins on a FinFET semiconductor deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 17, 2014·72 cites·13 claims
- 0597US9704973B2Methods of forming fins for FinFET semiconductor devices and the selective removal of such finsGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 11, 2017·19 cites·17 claims
- 0697US9431512B2Methods of forming nanowire devices with spacers and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 30, 2016·32 cites·19 claims
- 0797US9406775B1Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraintsGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 2, 2016·22 cites·15 claims
- 0897US8298885B2Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structureWEI ANDY·Filed 2010·Granted Oct 30, 2012·35 cites·16 claims
- 0996US9899268B2Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 20, 2018·14 cites·19 claims
- 1096US9159630B1Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask schemeGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 13, 2015·32 cites·20 claims
- 1196US8722498B2Self-aligned fin transistor formed on a bulk substrate by late fin etchSCHEIPER THILO·Filed 2011·Granted May 13, 2014·28 cites·20 claims
- 1295US9425097B1Cut first alternative for 2D self-aligned viaGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 23, 2016·12 cites·10 claims
- 1395US8557666B2Methods for fabricating integrated circuitsWEI ANDY C·Filed 2011·Granted Oct 15, 2013·32 cites·18 claims
- 1495US8114746B2Method for forming double gate and tri-gate transistors on a bulk substrateWEI ANDY·Filed 2009·Granted Feb 14, 2012·38 cites·28 claims
- 1595US8053273B2Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition processADVANCED MICRO DEVICES INC·Filed 2009·Granted Nov 8, 2011·32 cites·19 claims
- 1695US7399663B2Embedded strain layer in thin SOI transistors and a method of forming the sameADVANCED MICRO DEVICES INC·Filed 2006·Granted Jul 15, 2008·31 cites·18 claims
- 1794US9825031B1Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 21, 2017·23 cites·16 claims
- 1894US9202751B2Transistor contacts self-aligned in two dimensionsGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 1, 2015·13 cites·20 claims
- 1994US8609510B1Replacement metal gate diffusion break formationGLOBALFOUNDRIES INC·Filed 2012·Granted Dec 17, 2013·126 cites·20 claims
- 2094US7586153B2Technique for forming recessed strained drain/source regions in NMOS and PMOS transistorsADVANCED MICRO DEVICES INC·Filed 2006·Granted Sep 8, 2009·25 cites·17 claims
- 2194US7354838B2Technique for forming a contact insulation layer with enhanced stress transfer efficiencyADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 8, 2008·28 cites·19 claims
- 2294US7354839B2Gate structure and a transistor having asymmetric spacer elements and methods of forming the sameADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 8, 2008·40 cites·13 claims
- 2394US7138320B2Advanced technique for forming a transistor having raised drain and source regionsADVANCED MICRO DEVICES INC·Filed 2004·Granted Nov 21, 2006·82 cites·12 claims
- 2493US12211786B2Stacked vias with bottom portions formed using selective growthINTEL CORP·Filed 2021·Granted Jan 28, 2025·2 cites·20 claims
- 2593US9735154B2Semiconductor structure having gap fill dielectric layer disposed between finsGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 15, 2017·9 cites·20 claims
- 2693US9263325B1Precut metal linesGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 16, 2016·12 cites·20 claims
- 2793US8603893B1Methods for fabricating FinFET integrated circuits on bulk semiconductor substratesWEI ANDY C·Filed 2012·Granted Dec 10, 2013·56 cites·15 claims
- 2893US8241977B2Short channel transistor with reduced length variation by using amorphous electrode material during implantationSCHEIPER THILO·Filed 2010·Granted Aug 14, 2012·12 cites·19 claims
- 2993US7579262B2Different embedded strain layers in PMOS and NMOS transistors and a method of forming the sameADVANCED MICRO DEVICES INC·Filed 2006·Granted Aug 25, 2009·25 cites·23 claims
- 3092US9679805B2Self-aligned back end of line cutGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 13, 2017·7 cites·14 claims
- 3192US9117908B2Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor productsGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 25, 2015·11 cites·15 claims
- 3292US8071442B2Transistor with embedded Si/Ge material having reduced offset to the channel regionKRONHOLZ STEPHAN·Filed 2009·Granted Dec 6, 2011·22 cites·17 claims
- 3392US7723174B2CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistorGLOBALFOUNDRIES INC·Filed 2009·Granted May 25, 2010·25 cites·14 claims
- 3492US7329571B2Technique for providing multiple stress sources in NMOS and PMOS transistorsADVANCED MICRO DEVICES INC·Filed 2006·Granted Feb 12, 2008·24 cites·29 claims
- 3591US9306019B2Integrated circuits with nanowires and methods of manufacturing the sameGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 5, 2016·12 cites·16 claims
- 3691US9275890B2Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay markGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 1, 2016·10 cites·16 claims
- 3791US9236437B2Method for creating self-aligned transistor contactsGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·11 cites·8 claims
- 3891US8021942B2Method of forming CMOS device having gate insulation layers of different type and thicknessGLOBALFOUNDRIES INC·Filed 2008·Granted Sep 20, 2011·23 cites·22 claims
- 3991US7659213B2Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the sameGLOBALFOUNDRIES INC·Filed 2006·Granted Feb 9, 2010·20 cites·21 claims
- 4090US11482524B2Gate spacing in integrated circuit structuresINTEL CORP·Filed 2020·Granted Oct 25, 2022·2 cites·20 claims
- 4190US9660075B2Integrated circuits with dual silicide contacts and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2016·Granted May 23, 2017·5 cites·19 claims
- 4290US9508642B2Self-aligned back end of line cutGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 29, 2016·9 cites·17 claims
- 4390US9390979B2Opposite polarity borderless replacement metal contact schemeGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 12, 2016·9 cites·14 claims
- 4490US9196710B2Integrated circuits with relaxed silicon / germanium finsGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 24, 2015·11 cites·19 claims
- 4590US9177951B2Three-dimensional electrostatic discharge semiconductor deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·7 cites·12 claims
- 4690US8722500B2Methods for fabricating integrated circuits having gate to active and gate to gate interconnectsSCHEIPER THILO·Filed 2011·Granted May 13, 2014·10 cites·9 claims
- 4789US9397004B2Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openingsGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 19, 2016·10 cites·14 claims
- 4889US9105478B2Devices and methods of forming fins at tight fin pitchesGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 11, 2015·9 cites·10 claims
- 4989US8357978B1Methods of forming semiconductor devices with replacement gate structuresGLOBALFOUNDRIES INC·Filed 2011·Granted Jan 22, 2013·9 cites·13 claims
- 5088US9490340B2Methods of forming nanowire devices with doped extension regions and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 8, 2016·8 cites·19 claims
Showing the top 50 of 276 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Andy Wei files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →