Assignee
TERA SYSTEMS INC
US·3 granted patents·4 pending applications·474 citations·filing 1998–2005
Technology mixG06F7
Top patents by PatentIndex Score
7 records- 0197US6360356B1Creating optimized physical implementations from high-level descriptions of electronic design using placement-based informationTERA SYSTEMS INC·Filed 2000·Granted Mar 19, 2002·157 cites·92 claims
- 0295US6145117ACreating optimized physical implementations from high-level descriptions of electronic design using placement based informationTERA SYSTEMS INC·Filed 1998·Granted Nov 7, 2000·237 cites·37 claims
- 0394US7143367B2Creating optimized physical implementations from high-level descriptions of electronic design using placement-based informationTERA SYSTEMS INC·Filed 2001·Granted Nov 28, 2006·80 cites·35 claims
- 0449US2006053396A1Creating optimized physical implementations from high-level descriptions of electronic design using placement-based informationTERA SYSTEMS INC·Filed 2005·Application pending·0 cites
- 0541US2005268269A1Methods and systems for cross-probing in integrated circuit designTERA SYSTEMS INC·Filed 2005·Application pending·0 cites
- 0639US2005268258A1Rule-based design consultant and method for integrated circuit designTERA SYSTEMS INC·Filed 2005·Application pending·0 cites
- 0737US2005268268A1Methods and systems for structured ASIC electronic design automationTERA SYSTEMS INC·Filed 2005·Application pending·0 cites
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