Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information

Abstract

An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes a RTL model of an electronic design and maps it into an efficient, high level hierarchical representation of the hardware implementation of the design. Automatic partitioning partitions the hardware representation into functional partitions, and creates a fully characterized performance envelope for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations. In this fashion, a multiple-pass process converges on an optimal selection of physical implementations for all partitions for the entire chip that meet minimum timing requirements and other design goals. The system outputs specific control and data files which thoroughly define the implementation details of the design through the entire back-end flow process, thereby guaranteeing that the fabricated design meets all design goals without costly and time consuming design iterations.

1 . A method for transforming a logical hierarchy associated with a model of an electronic design into a physical hierarchy optimized for chip-level implementation of that electronic design, the method comprising: 
 partitioning the model into a number of data-flow-logic partitions and control logic partitions, each partition having a boundary; and    selectively readjusting partition boundaries in response to placement based information thereby forming a physical hierarchy based on connectivity between partitions.    
     
     
         2 . A method for partitioning an electronic design into a number of data-flow-logic partitions, the method of comprising: 
 traversing the electronic design to group data operators inter-connected by buses into data-flow-logic partitions, wherein data operators interconnected by an independent bus system form an independent data-flow partition; and    selectively breaking or merging each of the data-flow-logic partitions based on placement-based information.    
     
     
         3 . A method of creating logic building blocks for modeling the physical characteristics of an electronic design before gate-level implementation, the method comprising: 
 placing and routing a plurality of physical implementations for each logic structure in a plurality of logic structures;    measuring performance data of each physical implementation of each logic structure for the plurality of logic structures;    generating a plurality of placement based wire load models for the plurality of logic structures, wherein a placement based wire load model is created for each logic structure based on the measured performance data of each physical implementation of the logic structure; and    creating a library of logic building blocks from the plurality of placement based wire load models, wherein each logic building block includes data from a corresponding placement based wire load model.    
     
     
         4 . The method of  claim 3 , further comprising: 
 modeling the electronic design using a plurality of logic building blocks from the library of logic building blocks.    
     
     
         5 . The method of  claim 3 , further comprising: 
 characterizing the measured performance data of each physical implementation of each logic structure for random logic and datapath implementations,    wherein each logic building block further includes the characterized performance data of the corresponding logic structure.    
     
     
         6 . The method of  claim 3 , wherein each logic building block has multiple implementations representing different area and speed tradeoffs.