Assignee
VIA CYRIX INC
US·31 granted patents·3 pending applications·854 citations·filing 1993–2005
Top patents by PatentIndex Score
34 records- 0183US6351789B1Built-in self-test circuit and method for validating an associative data arrayVIA CYRIX INC·Filed 1998·Granted Feb 26, 2002·111 cites·22 claims
- 0279US6219773B1System and method of retiring misaligned write operands from a write bufferVIA CYRIX INC·Filed 1993·Granted Apr 17, 2001·79 cites·14 claims
- 0379US6138230AProcessor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipelineVIA CYRIX INC·Filed 1997·Granted Oct 24, 2000·88 cites·12 claims
- 0475US6239627B1Clock multiplier using nonoverlapping clock pulses for waveform generationVIA CYRIX INC·Filed 1997·Granted May 29, 2001·49 cites·3 claims
- 0574US6205560B1Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAGVIA CYRIX INC·Filed 1996·Granted Mar 20, 2001·76 cites·22 claims
- 0673US6005425APLL using pulse width detection for frequency and phase error correctionVIA CYRIX INC·Filed 1998·Granted Dec 21, 1999·38 cites·16 claims
- 0771US7013383B2Apparatus and method for managing a processor pipeline in response to exceptionsVIA CYRIX INC·Filed 2003·Granted Mar 14, 2006·17 cites·26 claims
- 0868US6351797B1Translation look-aside buffer for storing region configuration bits and method of operationVIA CYRIX INC·Filed 1998·Granted Feb 26, 2002·58 cites·14 claims
- 0966US5996071ADetecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target addressVIA CYRIX INC·Filed 1995·Granted Nov 30, 1999·52 cites·11 claims
- 1065US7177981B2Method and system for cache power reductionVIA CYRIX INC·Filed 2003·Granted Feb 13, 2007·10 cites·20 claims
- 1164US7143243B2Tag array access reduction in a cache memoryVIA CYRIX INC·Filed 2003·Granted Nov 28, 2006·13 cites·23 claims
- 1263US7024544B2Apparatus and method for accessing registers in a processorVIA CYRIX INC·Filed 2003·Granted Apr 4, 2006·8 cites·12 claims
- 1363US6073231APipelined processor with microcontrol of register translation hardwareVIA CYRIX INC·Filed 1997·Granted Jun 6, 2000·43 cites·7 claims
- 1461US6983359B2Processor and method for pre-fetching out-of-order instructionsVIA CYRIX INC·Filed 2003·Granted Jan 3, 2006·7 cites·17 claims
- 1558US6844767B2Hierarchical clock gating circuit and methodVIA CYRIX INC·Filed 2003·Granted Jan 18, 2005·10 cites·3 claims
- 1655US6065091ATranslation look-aside buffer slice circuit and method of operationVIA CYRIX INC·Filed 1997·Granted May 16, 2000·30 cites·40 claims
- 1753US6842052B2Multiple asynchronous switching systemVIA CYRIX INC·Filed 2002·Granted Jan 11, 2005·3 cites·21 claims
- 1850US7194601B2Low-power decode circuitry and method for a processor having multiple decodersVIA CYRIX INC·Filed 2003·Granted Mar 20, 2007·2 cites·16 claims
- 1950US6032241AFast RAM for use in an address translation circuit and method of operationVIA CYRIX INC·Filed 1997·Granted Feb 29, 2000·23 cites·23 claims
- 2049US6115730AReloadable floating point unitVIA CYRIX INC·Filed 1997·Granted Sep 5, 2000·24 cites·9 claims
- 2147US6301647B1Real mode translation look-aside buffer and method of operationVIA CYRIX INC·Filed 1997·Granted Oct 9, 2001·19 cites·21 claims
- 2247US2006136699A1Apparatus and method for accessing registers in a processorVIA CYRIX INC·Filed 2005·Application pending·0 cites
- 2346US6381622B1System and method of expediting bit scan instructionsVIA CYRIX INC·Filed 1996·Granted Apr 30, 2002·18 cites·18 claims
- 2445US6442635B1Processor architecture for virtualizing selective external bus transactionsVIA CYRIX INC·Filed 1998·Granted Aug 27, 2002·14 cites·14 claims
- 2543US7594103B1Microprocessor and method of processing instructions for responding to interrupt conditionVIA CYRIX INC·Filed 2002·Granted Sep 22, 2009·0 cites·20 claims
- 2643US6412063B1Multiple-operand instruction in a two operand pipeline and processor employing the sameVIA CYRIX INC·Filed 1999·Granted Jun 25, 2002·15 cites·20 claims
- 2743US2004230781A1Method and system for predicting the execution of conditional instructions in a processorVIA CYRIX INC·Filed 2003·Application pending·0 cites
- 2843US2004255103A1Method and system for terminating unnecessary processing of a conditional instruction in a processorVIA CYRIX INC·Filed 2003·Application pending·0 cites
- 2942US7130988B2Status register update logic optimizationVIA CYRIX INC·Filed 2002·Granted Oct 31, 2006·0 cites·10 claims
- 3040USRE39385EMethod and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplierVIA CYRIX INC·Filed 1993·Granted Nov 7, 2006·11 cites·43 claims
- 3137US6209083B1Processor having selectable exception handling modesVIA CYRIX INC·Filed 1997·Granted Mar 27, 2001·10 cites·18 claims
- 3236US6275926B1System and method for writing back multiple results over a single-result bus and processor employing the sameVIA CYRIX INC·Filed 1999·Granted Aug 14, 2001·8 cites·28 claims
- 3336US6009533ASpeculative bus cycle acknowledge for 1/2X core/bus clockingVIA CYRIX INC·Filed 1998·Granted Dec 28, 1999·12 cites·5 claims
- 3433US6169772B1Stretching setup and hold times in synchronous designsVIA CYRIX INC·Filed 1997·Granted Jan 2, 2001·6 cites·12 claims
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