Apparatus and method for accessing registers in a processor

Abstract

The present invention is generally directed to an apparatus and method for accessing registers within a processor. In accordance with one embodiment, an apparatus and method are provided for a processor in which at least two separate indicia (such as register select lines, register bank identifiers, processor mode identifiers, etc.) are utilized to uniquely identify and access a processor register. In accordance with this embodiment, bit lines of the separate indicia are encoded into a single, mapped set of signal lines, and these encoded signal lines are used to access the register.

1 - 7 . (canceled)  
   
   
       8 . A processor comprising: 
 a plurality w of registers arranged in a banked configuration, such that fewer than w registers are program-accessible to any single instruction operation;    logic configured to carry a register-select value defined by m bits;    logic configured to carry a register-bank value defined by n bits; and    encoder logic configured to encode register-select value with the register-bank value to generate a mapped value defined by p bits output from the encoder logic, where p is less than m+n, wherein a mapped value carried on the p bits uniquely identifies a register among the plurality w of registers.    
   
   
       9 . The processor of  claim 8 , further comprising circuitry for passing the mapped value to different pipelined stages of the processor along with data from a register uniquely identified by the mapped value.  
   
   
       10 . The processor of  claim 8 , further comprising data forwarding logic configured to compare the mapped value output from the encoder logic with at least one mapped value from a subsequent pipeline stage.  
   
   
       11 . The processor of  claim 10 , wherein the data forwarding logic includes logic for reading a data value associated with the mapped value output from the encoder from a register file, responsive to the logic configured to compare, if the mapped value output from the encoder logic does not match with the at least one mapped value from a subsequent pipeline stage.  
   
   
       12 . The processor of  claim 10 , wherein the data forwarding logic includes logic for reading a data value associated with the mapped value output from the encoder from a subsequent pipeline stage, responsive to the logic configured to compare, if the mapped value output from the encoder logic does match with the at least one mapped value from a subsequent pipeline stage.  
   
   
       13 . The processor of  claim 8 , wherein the logic having n bits comprises a component selected from the group consisting of: a register, a memory device, and a latch.  
   
   
       14 - 18 . (canceled)  
   
   
       19 . In a processor having w registers arranged in a banked configuration, such that fewer than w registers are accessible to any single instruction operation, a method comprising: 
 encoding a bank-select value carried on a plurality n of bank-identifying bit with a register value carried on a plurality m of register-select bits to produce a mapped value carried on a plurality p of bits, wherein p is less than the sum of n+m; and    using the encoded plurality of bits to uniquely access any of the w registers.    
   
   
       20 . The method of  claim 19 , further comprising passing the mapped value to different pipelined stages of the processor along with data from a register uniquely identified by the mapped value.  
   
   
       21 . The method of  claim 19 , further comprising comparing the mapped value output from the encoder logic with at least one mapped value from a subsequent pipeline stage.  
   
   
       22 . The method of  claim 21 , wherein the step of comparing further comprises reading a data value associated with the mapped value, if the mapped value output from the encoding step does not match with the at least one mapped value from a subsequent pipeline stage.  
   
   
       23 . The method of  claim 21 , further comprising reading a data value associated with the mapped value output from the encoder from a subsequent pipeline stage, if the mapped value output from the encoder logic does match with the at least one mapped value from a subsequent pipeline stage.