Inventor · disambiguated record
Charles Shelor
Also filed as: SHELOR CHARLES · SHELOR CHARLES F
13 granted patents·7 pending applications·219 citations·filing 1986–2006
91Inventor score
Top patents by PatentIndex Score
20 records- 0177US4807184AModular multiple processor architecture using distributed cross-point switchLTV AEROSPACE·Filed 1986·Granted Feb 21, 1989·67 cites·13 claims
- 0271US7013383B2Apparatus and method for managing a processor pipeline in response to exceptionsVIA CYRIX INC·Filed 2003·Granted Mar 14, 2006·17 cites·26 claims
- 0363US7024544B2Apparatus and method for accessing registers in a processorVIA CYRIX INC·Filed 2003·Granted Apr 4, 2006·8 cites·12 claims
- 0461US6661774B1System and method for traffic shaping packet-based signalsEFFICIENT NETWORKS INC·Filed 1999·Granted Dec 9, 2003·49 cites·44 claims
- 0559US6813249B1System and method for prefetching dataEFFICIENT NETWORKS INC·Filed 1999·Granted Nov 2, 2004·43 cites·39 claims
- 0658US6844767B2Hierarchical clock gating circuit and methodVIA CYRIX INC·Filed 2003·Granted Jan 18, 2005·10 cites·3 claims
- 0757US7552252B2Memory interface circuit and methodVIA TECH INC·Filed 2006·Granted Jun 23, 2009·1 cites·15 claims
- 0851US7363475B2Managing registers in a processor to emulate a portion of a stackVIA TECH INC·Filed 2004·Granted Apr 22, 2008·2 cites·6 claims
- 0950US7254670B2System, method, and apparatus for realizing quicker access of an element in a data structureVIA TECH INC·Filed 2004·Granted Aug 7, 2007·2 cites·17 claims
- 1050US7194601B2Low-power decode circuitry and method for a processor having multiple decodersVIA CYRIX INC·Filed 2003·Granted Mar 20, 2007·2 cites·16 claims
- 1147US2006136699A1Apparatus and method for accessing registers in a processorVIA CYRIX INC·Filed 2005·Application pending·0 cites
- 1245US7350059B2Managing stack transfers in a register-based processorVIA TECH INC·Filed 2004·Granted Mar 25, 2008·0 cites·20 claims
- 1343US6621824B1Data transmission system and method of operationEFFICIENT NETWORKS INC·Filed 1999·Granted Sep 16, 2003·18 cites·29 claims
- 1443US2004230781A1Method and system for predicting the execution of conditional instructions in a processorVIA CYRIX INC·Filed 2003·Application pending·0 cites
- 1543US2004255103A1Method and system for terminating unnecessary processing of a conditional instruction in a processorVIA CYRIX INC·Filed 2003·Application pending·0 cites
- 1642US7130988B2Status register update logic optimizationVIA CYRIX INC·Filed 2002·Granted Oct 31, 2006·0 cites·10 claims
- 1742US2004221117A1Logic and method for reading data from cacheFiled 2003·Application pending·0 cites
- 1842US2004205322A1Low-power decode circuitry for a processorFiled 2003·Application pending·0 cites
- 1940US2003108205A1System and method for providing encrypted data to a deviceFiled 2001·Application pending·0 cites
- 2038US2004199723A1Low-power cache and method for operating sameFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →