Inventor
LANDRY GREG J
US18 patents
Patents
18 patentsUS6134181AOct 17, 2000
Configurable memory block
CYPRESS SEMICONDUCTOR CORP67 citations95
US6563437B1May 13, 2003
Method and apparatus for using programmable logic device (PLD) logic for decompression of configuration data
CYPRESS SEMICONDUCTOR CORP24 citations92
US5835970ANov 10, 1998
Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
CYPRESS SEMICONDUCTOR CORP24 citations92
US7301370B1Nov 27, 2007
High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
CYPRESS SEMICONDUCTOR CORP20 citations88
US6507932B1Jan 14, 2003
Methods of converting and/or translating a layout or circuit schematic or netlist thereof to a simulation schematic or netlist, and/or of simulating function(s) and/or performance characteristic(s) of a circuit
CYPRESS SEMICONDUCTOR CORP27 citations86
US7616513B1Nov 10, 2009
Memory device, current sense amplifier, and method of operating the same
CYPRESS SEMICONDUCTOR CORP17 citations84
US6611935B1Aug 26, 2003
Method and system for efficiently testing circuitry
CYPRESS SEMICONDUCTOR CORP8 citations73
US6486712B1Nov 26, 2002
Programmable switch
CYPRESS SEMICONDUCTOR CORP12 citations73
US6466505B1Oct 15, 2002
Flexible input structure for an embedded memory
CYPRESS SEMICONDUCTOR CORP12 citations73
US6298005B1Oct 2, 2001
Configurable memory block
CYPRESS SEMICONDUCTOR CORP7 citations73
US6043684AMar 28, 2000
Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
CYPRESS SEMICONDUCTOR CORP7 citations73
US5903174AMay 11, 1999
Method and apparatus for reducing skew among input signals within an integrated circuit
CYPRESS SEMICONDUCTOR CORP7 citations73
US6333891B1Dec 25, 2001
Circuit and method for controlling a wordline and/or stabilizing a memory cell
CYPRESS SEMICONDUCTOR CORP6 citations70
US6088289AJul 11, 2000
Circuit and method for controlling a wordline and/or stabilizing a memory cell
CYPRESS SEMICONDUCTOR CORP7 citations70
US6411140B1Jun 25, 2002
Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
CYPRESS SEMICONDUCTOR CORP6 citations62
US7230856B1Jun 12, 2007
High-speed multiplexer latch
CYPRESS SEMICONDUCTOR CORP2 citations61
US7777521B2Aug 17, 2010
Method and circuitry to translate a differential logic signal to a CMOS logic signal
CYPRESS SEMICONDUCTOR CORP4 citations58
US7126398B1Oct 24, 2006
Method and an apparatus to generate static logic level output
CYPRESS SEMICONDUCTOR CORP1 citations51