Inventor

EVERS MARIUS

US32 patents

⚠️ This page may combine multiple inventors who share the name “EVERS MARIUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EVERS MARIUS

ADVANCED MICRO DEVICES INC

Selective use of taint protection during speculative execution

Processor-guided execution of offloaded instructions using fixed function operations

Taint protection during speculative execution

Low latency synchronization for operation cache and instruction cache fetching and decoding instructions

Method for selecting transistor threshold voltages in an integrated circuit

Processor-guided execution of offloaded instructions using fixed function operations

Retaining cache entries of a processor core during a powered-down state

Bandwidth increase in branch prediction unit and level 1 instruction cache

Selectively performing ahead branch prediction based on types of branch instructions

Using loop exit prediction to accelerate or suppress loop mode of a processor

Using loop exit prediction to accelerate or suppress loop mode of a processor

Instruction cache prefetch throttle

Tracking stores and loads by bypassing load store units

Dynamic evaluation and reconfiguration of a data prefetcher

Protection against branch target buffer poisoning by a management layer

Protection against branch target buffer poisoning by a management layer

Context partitioning of branch prediction structures

Using return address predictor to speed up control stack return address verification

Retaining cache entries of a processor core during a powered-down state

Storing incidental branch predictions to reduce latency of misprediction recovery

Branch target buffer with early return prediction

Processor with accelerated lock instruction operation

Merged branch target buffer entries

Scheduler queue assignment burst mode

Variable distance bypass between tag array and data array pipelines in a cache

Selectively performing ahead branch prediction based on types of branch instructions

Resource management for northbridge using tokens

Stride prefetching across memory pages

Method and apparatus for performing a bus lock and translation lookaside buffer invalidation

GLOBALFOUNDRIES INC

Token based power control mechanism

Branch predictor directed prefetch

SHEN GENE

Processing pipeline having stage-specific thread selection and method thereof