Merged branch target buffer entries

Abstract

Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

What is claimed is: 
     
       1. A method of merged branch target buffer entries, the method comprising:
 maintaining, in a branch target buffer, an entry corresponding to a first branch instruction, wherein the entry comprises a truncated first branch target address for the first branch instruction and a truncated second branch target address for a second branch instruction, wherein the truncated first branch target address and the truncated second branch target address are each allocated a different number of bits within the branch target buffer; and 
 accessing, based on the first branch instruction, the entry. 
 
     
     
       2. The method of  claim 1 , further comprising storing, based on the entry, data indicating the first branch target address and the second branch target address in a prediction queue. 
     
     
       3. The method of  claim 2 , wherein the prediction queue is communicatively coupled to an instruction fetch unit configured to load, based on the first branch target address and the second branch target address, a plurality of instructions. 
     
     
       4. The method of  claim 1 , further comprising:
 receiving a first redirect indicating the first branch instruction and the first branch target address; and 
 storing, in the branch target buffer, the entry as identifying the first branch target address. 
 
     
     
       5. The method of  claim 4 , further comprising:
 receiving a second redirect indicating the second branch instruction and the second branch target address; and 
 modifying the entry to identify the second branch target address and the first branch target address. 
 
     
     
       6. The method of  claim 5 , further comprising determining, based on one or more merging rules, to modify the entry to identify the second branch target address and the first branch target address. 
     
     
       7. The method of  claim 6 , wherein the one or more merging rules are based on at least one of: a branch type for the first branch instruction, a branch type for the second branch instruction, or an instruction address for the second branch instruction being included in a next prediction window succeeding a prediction window for the first branch instruction. 
     
     
       8. The method of  claim 6 , wherein determining to modify the entry to identify the second branch target address and the first branch target address is further based on a number of bits required to identify, in the entry, the first branch target address and the second branch target address. 
     
     
       9. An apparatus comprising:
 a branch target predictor for merged branch target buffer entries, the branch target predictor configured to: 
 maintain, in a branch target buffer, an entry corresponding to a first branch instruction, wherein the entry comprises a truncated first branch target address for the first branch instruction and a truncated second branch target address for a second branch instruction, wherein the truncated first branch target address and the truncated second branch target address are each allocated a different number of bits within the branch target buffer; and 
 access, based on the first branch instruction, the entry. 
 
     
     
       10. The apparatus of  claim 9 , further configured to store, based on the entry, data indicating the first branch target address and the second branch target address in a prediction queue. 
     
     
       11. The apparatus of  claim 10 , wherein the prediction queue is communicatively coupled to an instruction fetch unit configured to load, based on the first branch target address and the second branch target address, a plurality of instructions. 
     
     
       12. The apparatus of  claim 9 , further configured to:
 receive a first redirect indicating the first branch instruction and the first branch target address; and 
 store, in the branch target buffer, the entry as identifying the first branch target address. 
 
     
     
       13. The apparatus of  claim 12 , further configured to:
 receive a second redirect indicating the second branch instruction and the second branch target address; and 
 modify the entry to identify the second branch target address and the first branch target address. 
 
     
     
       14. The apparatus of  claim 13 , further configured to determine, based on one or more merging rules, to modify the entry to identify the second branch target address and the first branch target address. 
     
     
       15. The apparatus of  claim 14 , wherein the one or more merging rules are based on at least one of: a branch type for the first branch instruction, a branch type for the second branch instruction, or an instruction address for the second branch instruction being included in a next prediction window succeeding a prediction window for the first branch instruction. 
     
     
       16. The apparatus of  claim 14 , wherein determining to modify the entry to identify the second branch target address and the first branch target address is further based on a number of bits required to identify, in the entry, the first branch target address and the second branch target address. 
     
     
       17. A computing device comprising:
 a memory storing computer readable instructions; and 
 a processor in communication with said memory and comprising:
 a processor core including: 
 a branch target predictor for merged branch target buffer entries, the branch target predictor configured to:
 maintain, in a branch target buffer, an entry corresponding to a first branch instruction of said computer readable instructions, wherein the entry comprises a truncated first branch target address for the first branch instruction and a truncated second branch target address for a second branch instruction, wherein the truncated first branch target address and the truncated second branch target address are each allocated a different number of bits within the branch target buffer; and 
 access, based on the first branch instruction, the entry. 
 
 
 
     
     
       18. The computing device of  claim 17  wherein said processor comprises a system on a chip. 
     
     
       19. A method of operating a computing device for improved efficiency, the computing device comprising a memory and a processor in communication with said memory, said memory storing computer readable instructions executing on said processor, said method comprising:
 maintaining, in a branch target buffer of said processor, an entry corresponding to a first branch instruction of said computer readable instructions, wherein the entry comprises a truncated first branch target address for the first branch instruction and a truncated second branch target address for a second branch instruction, wherein the truncated first branch target address and the truncated second branch target address are each allocated a different number of bits within the branch target buffer; and 
 accessing, based on the first branch instruction, the entry. 
 
     
     
       20. The method of  claim 19 , further comprising storing, based on the entry, data indicating the first branch target address and the second branch target address in a prediction queue. 
     
     
       21. An apparatus for merged branch target buffer entries, comprising:
 a processor comprising a branch target predictor configured to:
 maintain, in a branch target buffer, an entry corresponding to a first branch instruction, wherein the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction, wherein the entry further includes a field identifying a type of instruction for the first branch instruction and a type of relationship between the first branch instruction and the second branch instruction, wherein the type of relationship indicates whether the second branch instruction is on a taken path of the first branch instruction or whether the first branch instruction is on a different prediction window than the second branch instruction; and 
 access, based on the first branch instruction, the entry. 
 
 
     
     
       22. The apparatus of  claim 21 , wherein the branch target predictor is further configured to store, based on the entry, data indicating the first branch target address and the second branch target address in a prediction queue. 
     
     
       23. The apparatus of  claim 21 , wherein the branch target predictor is further configured to:
 receive a first redirect indicating the first branch instruction and the first branch target address; and 
 store, in the branch target buffer, the entry as identifying the first branch target address. 
 
     
     
       24. The apparatus of  claim 21 , wherein the branch target predictor is further configured to:
 receive a second redirect indicating the second branch instruction and the second branch target address; and 
 modify the entry to identify the second branch target address and the first branch target address. 
 
     
     
       25. The apparatus of  claim 21 , wherein the branch target predictor is further configured to determine, based on one or more merging rules, to modify the entry to identify the second branch target address and the first branch target address. 
     
     
       26. The apparatus of  claim 25 , wherein the one or more merging rules are based on at least one of: a branch type for the first branch instruction, a branch type for the second branch instruction, or an instruction address for the second branch instruction being included in a next prediction window succeeding a prediction window for the first branch instruction. 
     
     
       27. The apparatus of  claim 21 , wherein determining to modify the entry to identify the second branch target address and the first branch target address is further based on a number of bits required to identify, in the entry, the first branch target address and the second branch target address.