Inventor

KIM YOUN CHEUL

US29 patents

⚠️ This page may combine multiple inventors who share the name “KIM YOUN CHEUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM YOUN CHEUL

SAMSUNG ELECTRONICS CO LTD

Semiconductor memory device and method of generating chip enable signal thereof

Duty cycle correction circuit of delay locked loop and the delay locked loop having the duty cycle correction circuit

Synchronous memory device

Multi-port semiconductor device and method thereof

Input receiver for controlling offset voltage using output feedback signal

Multi-port memory device and method of controlling the same

Delay locked loop having a duty cycle correction circuit

Memory module with parallel testing

Synchronous memory device

Semiconductor memory device using tapered arrangement of local input and output sense amplifiers

Memory device employing dual clocking for generating systematic code and method thereof

Input/output data pipeline circuit of semiconductor memory device and the semiconductor memory device

Memory module with parallel testing

SUNRISE MEMORY CORP

Quasi-volatile system-level memory

High capacity memory circuit with low effective latency

High capacity memory circuit with low effective latency

High capacity memory circuit with low effective latency

Quasi-volatile system-level memory

YANGTZE MEMORY TECH CO LTD

3D NAND memory device and method of forming the same

Structure and method for testing three-dimensional memory device

Structure and method for testing three-dimensional memory device

3D NAND memory device and method of forming the same

3D NAND memory device and method of forming the same

SK HYNIX INC

Semiconductor devices including E-fuse arrays

Power supply scheme for small swing data line and method of operating the same

Circuit for small swing data line and method of operating the same

Delay-locked loop having a loop bandwidth dependency on phase error

KIM YOUN-CHEUL

Delay-locked loop having loop bandwidth dependency on operating frequency

Delay-locked loop having a loop bandwidth dependency on phase error