3D NAND memory device and method of forming the same

Abstract

A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.

What is claimed is: 
     
       1. A method for manufacturing a semiconductor device, comprising:
 forming a first VIA that extends from a second side of a first substrate, wherein the first substrate has an opposing first side on which a memory stack is formed, and the memory stack includes (i) a doped region positioned in the first side of the first substrate and electrically coupled to, (ii) a plurality of word lines formed over the first side of the first substrate in a staircase configuration, and (iii) a plurality of insulating layers that are disposed between the plurality of word lines; 
 forming a first connection structure over the first VIA so that the first connection structure is coupled to the doped region through the first VIA; 
 forming a common source structure that is coupled to and extends from the doped region, and further extends through the plurality of word lines and the plurality of the insulating layers; and 
 forming a transistor that in a first side of a second substrate, wherein the first connection structure is coupled to the transistor. 
 
     
     
       2. The method of  claim 1 , wherein the forming the first connection structure over the first VIA further comprises:
 removing a portion of the first substrate from the second side of the first substrate; 
 forming the first VIA that extends from the second side of the first substrate to the doped region; and 
 forming the first connection structure over the first VIA. 
 
     
     
       3. The method of  claim 1 , further comprising:
 forming a spacer layer between the first VIA and the first substrate to isolate the first VIA from the first substrate. 
 
     
     
       4. The method of  claim 1 , further comprising:
 forming a n+ region between the first VIA and the doped region, the doped region being n-type. 
 
     
     
       5. The method of  claim 1 , wherein the first VIA has at least one of an extended wall-shape that has a tapered cross section or a frustoconical shape. 
     
     
       6. The method of  claim 1 , further comprising:
 forming a bonding VIA over and coupled to the transistor, and 
 bonding the first substrate and the second substrate through the bonding VIA, wherein the first side of the first substrate and the first side of the second substrate are aligned, face each other, and are bonded to each other by the bonding VIA. 
 
     
     
       7. The method of  claim 6 , further comprising:
 forming a through silicon VIA (TSV) that extends from the second side of the first substrate to the first side of the first substrate so as to be in contact with the bonding VIA, wherein the first connection structure is coupled to the transistor based on the TSV. 
 
     
     
       8. A semiconductor device, comprising:
 a first substrate having a first side for forming memory cells and a second side that is opposite to the first side; 
 a doped region formed in the first side of the first substrate; 
 a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, the first VIA extending from the second side of the first substrate to the doped region; and 
 a transistor formed in a first side of a second substrate and coupled to the first connection structure, wherein the memory cells further include: 
 a plurality of word lines formed over the first side of the first substrate in a staircase configuration, 
 a plurality of insulating layers that are disposed between the plurality of word lines, 
 a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers. 
 
     
     
       9. The semiconductor device of  claim 8 , further comprising:
 a spacer layer disposed between the first VIA and the first substrate that isolates the first VIA from the first substrate. 
 
     
     
       10. The semiconductor device of  claim 8 , further comprising:
 a n+ region arranged between the first VIA and the doped region, the doped region being n-type. 
 
     
     
       11. The semiconductor device of  claim 8 , wherein the first VIA has at least one of an extended wall-shape that has a tapered cross section or a frustoconical shape. 
     
     
       12. The semiconductor device of  claim 8 , wherein the first VIA extends through the doped region and is further in contact with the common source structure. 
     
     
       13. The semiconductor device of  claim 8 , further comprising:
 a bonding VIA formed over and coupled to the transistor, wherein the first side of the first substrate and the first side of the second substrate are aligned, face each other, and are bonded to each other by the bonding VIA. 
 
     
     
       14. The semiconductor device of  claim 13 , furthering comprising:
 a through silicon VIA (TSV) that extends from the second side of the first substrate to the first side of the first substrate so as to be in contact with the bonding VIA, wherein the first connection structure is coupled to the transistor based on the TSV. 
 
     
     
       15. The semiconductor device of  claim 8 , wherein the common source structure further extends along a direction parallel to the first side of the first substrate. 
     
     
       16. The semiconductor device of  claim 15 , further comprising:
 a plurality of channel structures extending from the first side of the first substrate, wherein:
 the plurality of channel structures extend through the plurality of word lines and the plurality of the insulation layers, and 
 the common source structure extends along the direction parallel to the first side of the first substrate to separate the plurality of the channel structures into sub-groups.