Inventor

MARIMUTHU PANDI CHELVAM

SG37 patents

⚠️ This page may combine multiple inventors who share the name “MARIMUTHU PANDI CHELVAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MARIMUTHU PANDI CHELVAM

STATS CHIPPAC LTD

Semiconductor device and method of forming an interposer package with through silicon vias

Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units

Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package

Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation

Method and apparatus for wafer level integration using tapered vias

Integrated circuit stacking system with integrated passive components

Solder bump confinement system for an integrated circuit package

Multi-leadframe semiconductor package and method of manufacture

Integrated circuit package system

Wafer integrated with permanent carrier and method therefor

Integrated circuit package system with interlock

LIN YAOJIAN

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

Semiconductor device and method of forming bump structure with multi-layer UBM around bump formation area

Integrated circuit package system with post-passivation interconnection and integration

Solder bump confinement system for an integrated circuit package

Semiconductor device and method of forming IPD in fan-out level chip scale package

Semiconductor device and method of forming IPD in fan-out wafer level chip scale package

Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP

Integrated passive device system

CHOI WON KYOUNG

Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

Integrated circuit system with debonding adhesive and method of manufacture thereof

Integrated circuit system with debonding adhesive and method of manufacture thereof

STATS CHIPPAC PTE LTD

Antenna in embedded wafer-level ball-grid array package

Antenna in embedded wafer-level ball-grid array package

Antenna in embedded wafer-level ball-grid array package

Method of packaging thin die and semiconductor device including thin die

MARIMUTHU PANDI CHELVAM

Semiconductor device and method of forming an interposer package with through silicon vias

Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support

KOO JUN MO

Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer

AHN BYUNG HOON

Integrated circuit leadframe and fabrication method therefor

GUILLERMO DENNIS

Integrated circuit package system with filled wafer recess

KOO JUNMO

Integrated circuit packaging system with transparent encapsulation and method of manufacture thereof

DO BYUNG TAI

Semiconductor device and method of providing common voltage bus and wire bondable redistribution

HAN BYUNG JOON

Wafer integrated with permanent carrier and method therefor

LIN YAOJIN

Integrated circuit package system with post-passivation interconnection and integration