Semiconductor device and method of forming an interposer package with through silicon vias

Abstract

A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL.

1. A method of making a semiconductor device, comprising:
 providing a carrier for supporting the semiconductor device; 
 mounting a first semiconductor die over the carrier; 
 mounting a first dummy die having a first through-silicon via (TSV) over the carrier; 
 encapsulating the first semiconductor die and the first dummy die using a wafer molding material; 
 removing the carrier; 
 forming a first redistribution layer (RDL) over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die; 
 forming an insulation layer over the first RDL; 
 forming a second RDL over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV; and 
 connecting a semiconductor package to the second RDL. 
 
     
     
       2. The method of  claim 1 , including:
 forming a second TSV in the first semiconductor die; 
 mounting a second semiconductor die over the first semiconductor die to connect to the second TSV; and 
 mounting a second dummy die over the first dummy die to connect to the first TSV. 
 
     
     
       3. The method of  claim 1 , including connecting the second RDL to a printed circuit board (PCB). 
     
     
       4. The method of  claim 1 , wherein the second RDL connects to a plurality of bumps. 
     
     
       5. The method of  claim 1 , wherein the first dummy die includes alignment markings to control placement of the first dummy die over the carrier. 
     
     
       6. The method of  claim 1 , wherein connecting the semiconductor package to the second RDL includes flip-chip mounting a second semiconductor die to the second RDL. 
     
     
       7. The method of  claim 6 , including thinning the wafer molding material to expose the second surface of the first dummy die and a second surface of the first semiconductor die opposite the first surface of the first semiconductor die. 
     
     
       8. A method of making a semiconductor device, comprising:
 providing a temporary carrier; 
 mounting a first semiconductor die over the temporary carrier; 
 mounting a first dummy die having a first through-silicon via (TSV) over the temporary carrier; 
 depositing encapsulant over the first semiconductor die and the first dummy die; 
 forming a first conductive layer electrically connected to the first semiconductor die and first TSV; and 
 forming a second conductive layer electrically connected to the first TSV. 
 
     
     
       9. The method of  claim 8 , including:
 forming a second TSV in the first semiconductor die; 
 mounting a second semiconductor die over the first semiconductor die to connect to the second TSV; and 
 mounting a second dummy die over the first dummy die to connect to the first TSV. 
 
     
     
       10. The method of  claim 8 , including thinning the encapsulant to expose a surface of the first semiconductor die and a surface of the first dummy die. 
     
     
       11. The method of  claim 8 , further including forming a plurality of bumps over the second conductive layer. 
     
     
       12. The method of  claim 8 , wherein the first dummy die includes alignment markings to control placement of the first dummy die over the temporary carrier. 
     
     
       13. The method of  claim 8 , including connecting the second conductive layer to a printed circuit board (PCB). 
     
     
       14. The method of  claim 8 , including connecting a semiconductor package to the second conductive layer. 
     
     
       15. The method of  claim 14 , wherein connecting the semiconductor package to the second conductive layer includes flip-chip mounting a second semiconductor die to the second conductive layer. 
     
     
       16. A method of making a semiconductor device, comprising:
 providing a carrier; 
 mounting a first semiconductor die over the carrier; 
 mounting a second semiconductor die including a conductive via over the carrier; 
 forming a first conductive layer connected to the first semiconductor die and the conductive via; and 
 forming a second conductive layer connected to the conductive via. 
 
     
     
       17. The method of  claim 16 , wherein the second semiconductor die includes alignment markings to control placement of the second semiconductor die over the carrier. 
     
     
       18. The method of  claim 16 , including connecting a semiconductor package to the second conductive layer. 
     
     
       19. The method of  claim 18 , wherein connecting a semiconductor package to the second conductive layer includes flip-chip mounting a third semiconductor die to the second conductive layer. 
     
     
       20. The method of  claim 19 , including connecting the second conductive layer to a printed circuit board (PCB). 
     
     
       21. A semiconductor device, comprising:
 a first semiconductor die; 
 a first dummy die including a through-silicon via (TSV) extending through the first dummy die such that the TSV has a first surface coplanar with a first surface of the first semiconductor die; 
 encapsulant deposited over and extends between the first semiconductor die and the first dummy die; 
 a first conductive layer formed over the first surface of the first semiconductor die and the first surface of the TSV to electrically connect the first semiconductor die and the TSV; and 
 a second conductive layer connected to a second surface of the TSV opposite the first surface of the TSV. 
 
     
     
       22. The semiconductor device of  claim 21 , further including:
 a second semiconductor die mounted over the first semiconductor die and electrically connected to the first semiconductor die; and 
 a second dummy die mounted over the first dummy die and electrically connected to the TSV. 
 
     
     
       23. The semiconductor device of  claim 21 , wherein the first dummy die includes alignment markings to control placement of the first dummy die. 
     
     
       24. The semiconductor device of  claim 21 , further including a semiconductor package connected to the second conductive layer. 
     
     
       25. The semiconductor device of  claim 24 , wherein the semiconductor package includes a second semiconductor die flip-chip mounted to the second conductive layer. 
     
     
       26. A semiconductor device, comprising:
 a first semiconductor die; 
 a first dummy die including a via that has a first surface coplanar with a first surface of the first semiconductor die; 
 a first conductive layer formed over the first surface of the first semiconductor die and the first surface of the via to electrically connect the first semiconductor die and the via; and 
 a second conductive layer connected to a second surface of the via opposite the first surface of the via. 
 
     
     
       27. The semiconductor device of  claim 26 , further including a semiconductor package connected to the second conductive layer. 
     
     
       28. The semiconductor device of  claim 26 , further including encapsulant deposited between the first semiconductor die and the first dummy die. 
     
     
       29. The semiconductor device of  claim 26 , further including:
 a second semiconductor die mounted over the first semiconductor die and electrically connected to the first semiconductor die; and 
 a second dummy die mounted over the first dummy die and electrically connected to the via. 
 
     
     
       30. The semiconductor device of  claim 26 , wherein the first dummy die includes alignment markings to control placement of the first dummy die. 
     
     
       31. The semiconductor device of  claim 26 , further including connecting the second conductive layer to a printed circuit board (PCB).