Inventor

CHRYSOS GEORGE Z

US36 patents

⚠️ This page may combine multiple inventors who share the name “CHRYSOS GEORGE Z”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHRYSOS GEORGE Z

INTEL CORP

Method and apparatus for preventing starvation in a slotted-ring network

Predictive early write-back of owned cache blocks in a shared memory computer system

Multiple dies hardware processors and methods

Supporting configurable security levels for memory address ranges

Supporting configurable security levels for memory address ranges

Memory sequencing with coherent and non-coherent sub-systems

Multiple dies hardware processors and methods

Tree-less integrity and replay memory protection for trusted execution environment

Method and apparatus for lockstep processing on a fixed-latency interconnect

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors

Method and apparatus for protecting TLB&#39;s VPN from soft errors

Method and apparatus for synchronous unbuffered flow control of packets on a ring interconnect

Memory sequencing with coherent and non-coherent sub-systems

Apparatus and method for efficient gather and scatter operations

COMPAQ COMPUTER CORP

Method for scheduling threads in a multithreaded processor

Apparatus and method for monitoring a computer system to guide optimization

Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline

Apparatus for sampling instruction execution information in a processor pipeline

Dynamically disabling speculative prefetch when high priority demand fetch opportunity use is high

Thread properties attribute vector based thread selection in multithreading processor

Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information

Dynamically inhibiting competing resource requesters in favor of above threshold usage requester to reduce response delay

Apparatus for determining the instantaneous average number of instructions processed

Apparatus for sampling path history in a processor pipeline

DIGITAL EQUIPMENT CORP

Apparatus for randomly sampling instructions in a processor pipeline

Method for estimating statistics of properties of instructions processed by a processor pipeline

Method and apparatus for predicting memory dependence using store sets

Apparatus for sampling instruction operand or result values in a processor pipeline

HEWLETT PACKARD DEVELOPMENT CO

Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU

STEELY JR SIMON C

Cache spill management techniques using cache spill prediction

GROCHOWSKI EDWARD T

Generational thread scheduler using reservations for fair scheduling

MATTINA MATTHEW

Protocol for maintaining cache coherency in a CMP

WANG HONG

Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors

CORBAL JESUS

Prefetch with request for ownership without data

Method and apparatus for protecting TLB's VPN from soft errors