Inventor
MILLER GAYLE W
US49 patents
⚠️ This page may combine multiple inventors who share the name “MILLER GAYLE W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
22 patentsUS6277707B1Aug 21, 2001
Method of manufacturing semiconductor device having a recessed gate structure
LSI LOGIC CORP58 citations96
US6130117AOct 10, 2000
Simple bicmos process for creation of low trigger voltage SCR and zener diode pad protection
LSI LOGIC CORP53 citations96
US6057571AMay 2, 2000
High aspect ratio, metal-to-metal, linear capacitor for an integrated circuit
LSI LOGIC CORP58 citations96
US6794310B1Sep 21, 2004
Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof
LSI LOGIC CORP17 citations93
US6328802B1Dec 11, 2001
Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof
LSI LOGIC CORP17 citations93
US6383332B1May 7, 2002
Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint
LSI LOGIC CORP20 citations92
US6358819B1Mar 19, 2002
Dual gate oxide process for deep submicron ICS
LSI LOGIC CORP32 citations92
US6117779ASep 12, 2000
Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint
LSI LOGIC CORP17 citations92
US6090724AJul 18, 2000
Method for composing a thermally conductive thin film having a low dielectric property
LSI LOGIC CORP25 citations92
US6258205B1Jul 10, 2001
Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material
LSI LOGIC CORP17 citations91
US6080670AJun 27, 2000
Method of detecting a polishing endpoint layer of a semiconductor wafer which includes a non-reactive reporting specie
LSI LOGIC CORP31 citations91
US6071818AJun 6, 2000
Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material
LSI LOGIC CORP22 citations91
US6319793B1Nov 20, 2001
Circuit isolation utilizing MeV implantation
LSI LOGIC CORP18 citations90
US6358837B1Mar 19, 2002
Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit
LSI LOGIC CORP16 citations84
US6136719AOct 24, 2000
Method and arrangement for fabricating a semiconductor device
LSI LOGIC CORP18 citations84
US6885078B2Apr 26, 2005
Circuit isolation utilizing MeV implantation
LSI LOGIC CORP19 citations82
US6287987B1Sep 11, 2001
Method and apparatus for deposition of porous silica dielectrics
LSI LOGIC CORP7 citations74
US6206573B1Mar 27, 2001
High reliability bearing structure
LSI LOGIC CORP9 citations74
US6150175ANov 21, 2000
Copper contamination control of in-line probe instruments
LSI LOGIC CORP9 citations74
US6806162B1Oct 19, 2004
Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device
LSI LOGIC CORP3 citations63
US6614097B1Sep 2, 2003
Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device
LSI LOGIC CORP2 citations63
US6268224B1Jul 31, 2001
Method and apparatus for detecting an ion-implanted polishing endpoint layer within a semiconductor wafer
LSI LOGIC CORP6 citations62
NCR CO
8 patentsUS4703551ANov 3, 1987
Process for forming LDD MOS/CMOS structures
NCR CO71 citations96
US4647340AMar 3, 1987
Programmable read only memory using a tungsten fuse
NCR CO63 citations95
US4679299AJul 14, 1987
Formation of self-aligned stacked CMOS structures by lift-off
NCR CO25 citations92
US4682404AJul 28, 1987
MOSFET process using implantation through silicon
NCR CO30 citations91
US4654121AMar 31, 1987
Fabrication process for aligned and stacked CMOS devices
NCR CO45 citations91
US4648175AMar 10, 1987
Use of selectively deposited tungsten for contact formation and shunting metallization
NCR CO44 citations91
US5322805AJun 21, 1994
Method for forming a bipolar emitter using doped SOG
NCR CO8 citations74
US5308790AMay 3, 1994
Selective sidewall diffusion process using doped SOG
NCR CO5 citations63
AT & T GLOBAL INF SOLUTION
7 patentsUS5581861ADec 10, 1996
Method for making a solid-state ink jet print head
AT & T GLOBAL INF SOLUTION49 citations96
US5459501AOct 17, 1995
Solid-state ink-jet print head
AT & T GLOBAL INF SOLUTION84 citations96
US5672905ASep 30, 1997
Semiconductor fuse and method
AT & T GLOBAL INF SOLUTION23 citations93
US5447880ASep 5, 1995
Method for forming an amorphous silicon programmable element
AT & T GLOBAL INF SOLUTION20 citations92
US5438022AAug 1, 1995
Method for using low dielectric constant material in integrated circuit fabrication
AT & T GLOBAL INF SOLUTION20 citations92
US5543361AAug 6, 1996
Process for forming titanium silicide local interconnect
AT & T GLOBAL INF SOLUTION7 citations74
US5443996AAug 22, 1995
Process for forming titanium silicide local interconnect
AT & T GLOBAL INF SOLUTION7 citations74
HYUNDAI ELECTRONICS AMERICA
7 patentsUS5963825AOct 5, 1999
Method of fabrication of semiconductor fuse with polysilicon plate
HYUNDAI ELECTRONICS AMERICA16 citations74
US6522005B1Feb 18, 2003
Integrated circuit device comprising low dielectric constant material for reduced cross talk
HYUNDAI ELECTRONICS AMERICA5 citations73
US6448653B1Sep 10, 2002
Method for using low dielectric constant material in integrated circuit fabrication
HYUNDAI ELECTRONICS AMERICA3 citations73
US6208029B1Mar 27, 2001
Integrated circuit device with reduced cross talk
HYUNDAI ELECTRONICS AMERICA8 citations73
US6504250B1Jan 7, 2003
Integrated circuit device with reduced cross talk
HYUNDAI ELECTRONICS AMERICA2 citations62
US6504249B1Jan 7, 2003
Integrated circuit device with reduced cross talk
HYUNDAI ELECTRONICS AMERICA1 citations62
US6522006B1Feb 18, 2003
Low dielectric constant material in integrated circuit
HYUNDAI ELECTRONICS AMERICA0 citations52