Inventor

BERTIN CLAUDE LOUIS

US51 patents

Patents

50 patents

US6410431B2Jun 25, 2002

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

IBM127 citations99

US6294406B1Sep 25, 2001

Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

IBM158 citations99

US5781031AJul 14, 1998

Programmable logic array

IBM472 citations99

US5731945AMar 24, 1998

Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

IBM126 citations99

US5648684AJul 15, 1997

Endcap chip with conductive, monolithic L-connect for multichip stack

IBM143 citations99

US5502333AMar 26, 1996

Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit

IBM389 citations99

US6141245AOct 31, 2000

Impedance control using fuses

IBM142 citations98

US5946545AAug 31, 1999

Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit

IBM98 citations98

US5943254AAug 24, 1999

Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

IBM171 citations98

US5907178AMay 25, 1999

Multi-view imaging apparatus

IBM108 citations98

US5786628AJul 28, 1998

Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging

IBM127 citations98

US5702984ADec 30, 1997

Integrated mulitchip memory module, structure and fabrication

IBM163 citations98

US5670803ASep 23, 1997

Three-dimensional SRAM trench structure and fabrication method therefor

IBM140 citations98

US6345362B1Feb 5, 2002

Managing Vt for reduced power using a status table

IBM139 citations97

US5869896AFeb 9, 1999

Packaged electronic module and integral sensor array

IBM97 citations97

US5719438AFeb 17, 1998

Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging

IBM97 citations97

US6444490B2Sep 3, 2002

Micro-flex technology in semiconductor packages

IBM45 citations96

US6388198B1May 14, 2002

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

IBM95 citations96

US6222276B1Apr 24, 2001

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

IBM82 citations96

US6219215B1Apr 17, 2001

Chip thermal protection device

IBM65 citations96

US5956575ASep 21, 1999

Microconnectors

IBM52 citations96

US5909400AJun 1, 1999

Three device BICMOS gain cell

IBM67 citations96

US6239649B1May 29, 2001

Switched body SOI (silicon on insulator) circuits and fabrication method therefor

IBM78 citations95

US5763943AJun 9, 1998

Electronic modules with integral sensor arrays

IBM54 citations95

US6943452B2Sep 13, 2005

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

IBM47 citations94

US5811868ASep 22, 1998

Integrated high-performance decoupling capacitor

IBM94 citations94

US5955818ASep 21, 1999

Machine structures fabricated of multiple microstructure layers

IBM32 citations93

US5763318AJun 9, 1998

Method of making a machine structures fabricated of mutiple microstructure layers

IBM36 citations93

US6300687B1Oct 9, 2001

Micro-flex technology in semiconductor packages

IBM28 citations92

US6243283B1Jun 5, 2001

Impedance control using fuses

IBM42 citations92

US6174763B1Jan 16, 2001

Three-dimensional SRAM trench structure and fabrication method therefor

IBM21 citations92

US5798282AAug 25, 1998

Semiconductor stack structures and fabrication sparing methods utilizing programmable spare circuit

IBM22 citations92

US5656544AAug 12, 1997

Process for forming a polysilicon electrode in a trench

IBM39 citations92

US6531410B2Mar 11, 2003

Intrinsic dual gate oxide MOSFET using a damascene gate process

IBM35 citations91

US5923181AJul 13, 1999

Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module

IBM41 citations90

US5880988AMar 9, 1999

Reference potential for sensing data in electronic storage element

IBM36 citations90

US5686843ANov 11, 1997

Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module

IBM30 citations90

US7276775B2Oct 2, 2007

Intrinsic dual gate oxide MOSFET using a damascene gate process

IBM15 citations82

US6570806B2May 27, 2003

System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor

IBM17 citations79

US5804464ASep 8, 1998

Semiconductor chip kerf clear method for forming semiconductor chips and electronic module therefore

IBM8 citations73

US5712190AJan 27, 1998

Process for controlling distance between integrated circuit chips in an electronic module

IBM9 citations73

US5670428ASep 23, 1997

Semiconductor chip kerf clear method and resultant semiconductor chip and electronic module formed from the same

IBM6 citations73

US5644162AJul 1, 1997

Semiconductor chip having chip metal layer and transfer metal layer composed of same metal, and corresponding electronic module

IBM9 citations73

US6433618B1Aug 13, 2002

Variable power device with selective threshold control

IBM8 citations72

US6339559B1Jan 15, 2002

Decode scheme for programming antifuses arranged in banks

IBM9 citations72

US6255208B1Jul 3, 2001

Selective wafer-level testing and burn-in

IBM10 citations72

Showing the top 50 of 51 patents by PatentIndex Score.

BERTIN CLAUDE LOUIS

Patents

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Highly integrated chip-on-chip packaging

Highly integrated chip-on-chip packaging

Microconnectors

Chip function separation onto separate stacked chips

Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

Programmable logic array

Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

Endcap chip with conductive, monolithic L-connect for multichip stack

Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit

Impedance control using fuses

Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit

Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

Multi-view imaging apparatus

Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging

Integrated mulitchip memory module, structure and fabrication

Three-dimensional SRAM trench structure and fabrication method therefor

Managing Vt for reduced power using a status table

Packaged electronic module and integral sensor array

Method and workpiece for connecting a thin layer to a monolithic electronic module&#39;s surface and associated module packaging

Micro-flex technology in semiconductor packages

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Chip thermal protection device

Microconnectors

Three device BICMOS gain cell

Switched body SOI (silicon on insulator) circuits and fabrication method therefor

Electronic modules with integral sensor arrays

Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality

Integrated high-performance decoupling capacitor

Machine structures fabricated of multiple microstructure layers

Method of making a machine structures fabricated of mutiple microstructure layers

Micro-flex technology in semiconductor packages

Impedance control using fuses

Three-dimensional SRAM trench structure and fabrication method therefor

Semiconductor stack structures and fabrication sparing methods utilizing programmable spare circuit

Process for forming a polysilicon electrode in a trench

Intrinsic dual gate oxide MOSFET using a damascene gate process

Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module

Reference potential for sensing data in electronic storage element

Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module

Intrinsic dual gate oxide MOSFET using a damascene gate process

System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor

Semiconductor chip kerf clear method for forming semiconductor chips and electronic module therefore

Process for controlling distance between integrated circuit chips in an electronic module

Semiconductor chip kerf clear method and resultant semiconductor chip and electronic module formed from the same

Semiconductor chip having chip metal layer and transfer metal layer composed of same metal, and corresponding electronic module

Variable power device with selective threshold control

Decode scheme for programming antifuses arranged in banks

Selective wafer-level testing and burn-in

Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging