Inventor

CRONIN JOHN EDWARD

US55 patents

⚠️ This page may combine multiple inventors who share the name “CRONIN JOHN EDWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRONIN JOHN EDWARD

IBM

Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same

Chip function separation onto separate stacked chips

Programmable logic array

Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging

Three-dimensional SRAM trench structure and fabrication method therefor

Method and workpiece for connecting a thin layer to a monolithic electronic module&#39;s surface and associated module packaging

Methods for precise definition of integrated circuit chip edges

Microconnectors

Semiconductor structure having multiple levels of self-aligned interconnection metallization, and methods for its preparation

Method for forming semiconductor chip and electronic module with integrated surface interconnects/components

Methods for precise definition of integrated circuit chip edges

Method for etching vertical contact holes without substrate damage caused by directional etching

Semiconductor device with increased on chip decoupling capacitance

Sidewall spacer using an overhang

Methods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization

Machine structures fabricated of multiple microstructure layers

Process of making a microcavity structure and applications thereof

Method of making a machine structures fabricated of mutiple microstructure layers

Integrated circuit contacts having resistive electromigration characteristics

Integrated circuit contacts having improved electromigration characteristics and fabrication methods therefor

Three-dimensional SRAM trench structure and fabrication method therefor

Self-aligned metallurgy

Refractory metal-titanium nitride conductive structures

Process for forming a polysilicon electrode in a trench

Inorganic seal for encapsulation of an organic layer and method for making the same

Inorganic seal for encapsulation of an organic layer and method for making the same

Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses

Gate stack structure of a field effect transistor

Process for metallization of an insulation layer

Variable travel carrier device and method for planarizing semiconductor wafers

Specially shaped contact via and integrated circuit therewith

Method of making a chimney capacitor

Self-aligned metallurgy

Stacked electrical device having regions of electrical isolation and electrical connections on a given stack level

Process for controlling distance between integrated circuit chips in an electronic module

Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same

DRAM cell with stacked capacitor self-aligned to bitline

Vertical mask for defining a region on a wall of a semiconductor structure

Semiconductor device with increased on chip decoupling capacitance

Method for defining a region on a wall of a semiconductor structure

Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses

WELLS FARGO BANK NA

Device enabled identification and authentication

Smart thermostat control system

Smart thermostat control system

Optimized product preparation

Incentives for physical activity

E INK CORP

Electro-optic displays, and methods for driving same

IP CAPITAL GROUP INC

Method of researching and analyzing information contained in a database

CRONIN JOHN EDWARD

System and method for sensing and managing pothole location and pothole characteristics

GARLAND STEPHEN DOUGLAS

System and method for controlling an asphalt repair apparatus

Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging