Inventor

LEUNG WINGYU

US98 patents

⚠️ This page may combine multiple inventors who share the name “LEUNG WINGYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEUNG WINGYU

MONOLITHIC SYSTEM TECH INC

Memory array with read/write methods

Dynamic address mapping and redundancy in a modular memory device

Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system

Method and apparatus for complete hiding of the refresh of a semiconductor memory

Circuit module redundancy architecture process

Method and structure for implementing a cache memory using a DRAM array

Fault-tolerant hierarchical bus system and method of operating same

Resynchronization circuit for a memory system and method of operating same

Circuit module redundancy architecture

Reduced CMOS-swing clamping circuit for bus lines

DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

Termination circuit with power-down mode for use in circuit module architecture

Caching method and circuit for a memory system with circuit module architecture

DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Method and apparatus for completely hiding refresh operations in a dram device using clock division

Reduced topography DRAM cell fabricated using a modified logic process and method for operating same

Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same

High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process

Method of operating memory array with write buffers and related apparatus

Data processing system with master and slave devices and asymmetric signal swing bus

Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices

On-chip word line voltage generation for DRAM embedded in logic process

System utilizing a DRAM array as a next level cache memory and method for operating same

Method and apparatus for increasing the time available for refresh for 1-t SRAM compatible devices

Method and apparatus for 1-T SRAM compatible memory

Termination circuits for reduced swing signal lines and methods for operating same

Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors

Caching in a multi-processor computer system

Transparent error correcting memory that supports partial-word write

Error correcting memory and method of operating same

Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage

DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Non-volatile memory embedded in a conventional logic process

Apparatus for controlling data transfer between a bus and memory array and method for operating same

DRAM cell fabricated using a modified logic process and method for operating same

Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory

Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory

RAMBUS INC

Method and circuitry for clock synchronization

Electrical current source circuitry for a bus

Method and circuitry for minimizing clock-data skew in a bus system

Delay stage circuitry for a ring oscillator

Delay stage circuitry for a ring oscillator

MOSYS INC

Method and structure for performing pipeline burst accesses in a semiconductor memory

Error detection/correction method

Dual-port SRAM memory using single-port memory cell

Word line driver for DRAM embedded in a logic process

INTEGRATED DEVICE TECH

High density SRAM circuit with ratio independent memory cells

MONOLITHIC SYSTEMS INC

Multi-port DRAM cell and memory system using same

MONOLITHIC SYSTEM TECHNOLOGY

High density SRAM circuit with single-ended memory cells