USRE38482EExpiredUtilityPatentIndex 96
Delay stage circuitry for a ring oscillator
Est. expiryMay 28, 2012(expired)· nominal 20-yr term from priority
H03L 7/0996H03L 7/06H03L 7/07H03K 3/0231H03K 3/354
96
PatentIndex Score
57
Cited by
63
References
103
Claims
Abstract
A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
(A) a differential amplifier for generating a differential output signal comprising a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:
(i) a first transistor coupled to the first node;
(ii) a second transistor coupled to the second node and the first transistor, wherein the first and second transistors are biased by an output level biasing voltage;
(iii) a third transistor coupled to the first node, wherein the third transistor receives a first input signal from a preceding delay stage;
(iv) a fourth transistor coupled to the second node and the third transistor, wherein the fourth transistor receives a second input signal from the preceding delay stage;
(B) a self-biased voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal; and
(C) a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.
2. The ring oscillator of claim 1 , wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
3. The ring oscillator of claim 2 , wherein the first and second diode-coupled transistor are metal-oxide semiconductor transistors.
4. The ring oscillator of claim 2 , wherein the first and second diode-coupled transistors are N-type transistors.
5. The ring oscillator of claim 1 , wherein the current source further comprises a fifth transistor.
6. The ring oscillator of claim 1 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.
7. The ring oscillator of claim 6 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.
8. The ring oscillator of claim 6 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.
9. The ring oscillator of claim 6 wherein the first and second types are complementary.
10. The ring oscillator of claim 1 wherein each delay stage further comprises a source follower buffer.
11. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
(A) a differential amplifier for generating a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:
(i) a first transistor coupled between the first node and a first potential;
(ii) a second transistor coupled between the second node and the first potential, wherein the first and second transistors are biased by an output level biasing voltage;
(iii) a third transistor coupled between the first node and a third node, wherein the third transistor receives a first input signal from a preceding delay stage;
(iv) a fourth transistor coupled between the second node and the third node, wherein the fourth transistor receives a second input signal from the preceding delay stage;
(B) a current source coupled between the third node and a second potential, the current source varying a bias current through the current source in accordance with a delay bias voltage; and
(C) a voltage clamping circuit coupled to the first and second nodes to limit a relative peak-to-peak voltage swing of the first and second output signals without independently clamping each of the first and second nodes.
12. The ring oscillator of claim 11 , wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
13. The ring oscillator of claim 12 , wherein the first and second diode-coupled transistors are metal-oxide semiconductor transistors.
14. The ring oscillator of claim 12 , wherein the first and second diode-coupled transistors are N-type transistors.
15. The ring oscillator of claim 11 , wherein the current source further comprises a fifth transistor.
16. The ring oscillator of claim 11 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.
17. The ring oscillator of claim 16 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.
18. The ring oscillator of claim 16 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.
19. The ring oscillator of claim 16 wherein the first and second types are complementary.
20. The ring oscillator of claim 11 wherein each delay stage further comprises a source follower buffer.
21. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
a differential amplifier providing a differential output signal;
a self-biased voltage clamping circuit coupled to limit a peak-to-peak voltage swing of the differential output signal; and
a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.
22. The ring oscillator of claim 21 , wherein the differential amplifier provides a first output signal at a first node and a second output signal at a second node, the first and second output signal forming the differential output signal, wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
23. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
a differential amplifier providing a differential output signal comprising a first output signal at a first node and a second output signal at a second node;
a voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal without independently clamping each of the first and second nodes; and
a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.
24. The ring oscillator of claim 23 , wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
25. A synchronous memory device comprising:
an array of memory cells to store data;
a clock synchronization loop to generate a plurality of clock signals, each clock signal having a timing relationship with respect to a reference clock signal;
first interpolator circuitry to generate a first internal clock signal from a first and a second clock signal of the plurality of clock signals, wherein a phase of the first internal clock signal is interpolated from respective phases of the first and second clock signals according to phase information indicative of whether the first internal clock signal leads or lags a first external clock signal; and
interface circuitry to synchronize a transmission of data with the first internal clock signal.
26. The memory device of claim 25 wherein the clock synchronization loop is a phase locked loop circuit.
27. The memory device of claim 25 wherein the timing relationship of each one of the plurality of clock signals is a respective phase offset from a phase of the reference clock signal.
28. The memory device of claim 25 wherein the clock synchronization loop comprises a plurality of delay elements coupled in series, each delay element outputting at least one of the plurality of clock signals.
29. The memory device of claim 28 wherein the plurality of delay elements in an even number of delay elements.
30. The memory device of claim 25 further comprising selection circuitry, coupled to the clock synchronization loop, to select the first and second clock signals from the plurality of clock signals.
31. The memory device of claim 30 further comprising:
a detector circuit to detect a phase polarity between the first internal clock signal and the first external clock signal;
a shift register, coupled in parallel with the selection circuitry, to output selection signals that control selection of the first and second clock signals; and
a control circuit to provide shift information to the shift register based on the phase polarity such that the selection signals output by the shift register select clock signals of the plurality of clock signals that have phases neighboring, on respective either sides, the phase of the first external clock signal.
32. The memory device of claim 25 , further comprising:
a detector circuit, coupled to the first interpolator circuitry, to detect the phase information; and
a control circuit to generate a control voltage that is responsive to the phase information, wherein the first interpolator circuitry steers the phase of the first internal clock signal between the phase of the first and second clock signals in response to the control voltage.
33. The memory device of claim 32 wherein after detection the phase information is represented by a binary value.
34. The memory device of claim 32 wherein the control circuit comprises:
a digital counter to generate a digital count value in response to the phase information; and
a digital to analog converter to generate the control voltage from the digital count value.
35. The memory device of claim 25 further comprising a buffer circuit to receive a second external clock signal and generate the reference clock signal using the second external clock signal.
36. The memory device of claim 35 wherein a reception of data is synchronized with the second external clock signal.
37. The memory device of claim 35 wherein the plurality of clock signals comprises a clock signal that is in phase with the second external clock signal.
38. The memory device of claim 25 further comprising second interpolator circuitry to generate a second internal clock signal from a pair of clock signals of the plurality of clock signals, wherein a phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals according to phase information indicative of whether the second internal clock signal leads or lags a second external clock signal.
39. The memory device of claim 25 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.
40. An integrated circuit device comprising:
interface circuitry to receive first and second external clock signals; and
clock synchronization circuitry to synchronize a transmission of data with the first external clock signal and to synchronize a reception of data with the second external clock signal, the clock synchronization circuitry including:
a reference loop to receive a reference clock signal and generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined timing relationship with the reference clock signal;
a first subloop circuit, coupled to the reference loop, to synchronize the transmission of data with the first external clock signal using the plurality of clock signals; and
a second subloop circuit, coupled to the reference loop, to synchronize the reception of data with the second external clock signal using the plurality of clock signals.
41. The integrated circuit device of claim 40 wherein the first subloop circuit generates an internal transmit clock signal having a phase relationship with respect to the first external clock signal.
42. The integrated circuit device of claim 41 wherein the phase relationship is a quadrature relationship.
43. The integrated circuit device of claim 41 wherein the internal transmit clock is in phase with the first external clock signal.
44. The integrated circuit device of claim 40 wherein the first subloop circuit further comprises:
selection circuitry to select first and second clock signals of the plurality of clock signals;
interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal transmit clock signal in response to a control signal, wherein the control signal steers the phase of the internal transmit clock signal between respective phases of the first and second clock signals; and
detector circuitry to detect phase information indicative of whether the internal transmit clock signal leads or lags the first external clock signal, and to generate the control signal using the phase information.
45. The integrated circuit device of claim 40 wherein the second subloop circuit generates an internal receive clock signal having a phase relationship with respect to the second external clock signal.
46. The integrated circuit device of claim 45 wherein the internal receive clock signal is in phase with the second external clock signal.
47. The integrated circuit device of claim 40 wherein the second subloop circuit further comprises:
selection circuitry to select first and second clock signals of the plurality of clock signals;
interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal receive clock signal in response to a control signal, wherein the control signal steers the phase of the internal receive clock signal between respective phases of the first and second clock signals; and
detector circuitry to detect phase information indicative of whether the internal receive clock signal leads or lags the second external clock signal, and to generate the control signal using the phase information.
48. The integrated circuit device of claim 40 wherein a first clock signal of the plurality of clock signals is in phase with the second external clock signal, and the other clock signals of the plurality of clock signals have respective phases that are evenly spaced across a clock period of the second external clock signal.
49. The integrated circuit device of claim 40 wherein the reference loop is a phase locked loop circuit.
50. The integrated circuit device of claim 40 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.
51. The integrated circuit device of claim 40 further comprising a buffer circuit to receive the second external clock signal and to generate the reference clock signal from the second external clock signal.
52. A clock synchronization circuit comprising:
a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a delay time with respect to a reference clock signal;
interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether a phase of the first clock signal leads or lags a phase of an input clock signal; and
a detector circuit to compare the phase of the first clock signal with the phase of the input clock signal, to generate the information indicative of whether the phase of the first clock signal leads or lags the phase of the input clock signal.
53. The clock synchronization circuit of claim 52 wherein the plurality of delay stages is an even number of delay stages.
54. The clock synchronization circuit of claim 52 further comprising a buffer to output the reference clock signal, wherein the buffer receives the input clock signal.
55. The clock synchronization circuit of claim 52 wherein each delay stage of the plurality of delay stages comprises:
a first output terminal;
a second output terminal;
a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and
a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.
56. The clock synchronization circuit of claim 52 wherein the plurality of delay stages is included in a phase locked loop circuit.
57. The clock synchronization circuit of claim 52 further comprising selection circuitry to select the pair of clock signals from the plurality of clock signals.
58. The clock synchronization circuit of claim 52 wherein the detector circuit comprises a phase detector to compare the phase of the first clock signal with the phase of the input clock signal, the phase detector to generate a binary signal that indicates whether the first clock signal leads or lags the input clock signal.
59. The clock synchronization circuit of claim 52 wherein the detector circuit comprises:
a counter circuit to change a count value in a first direction when the phase of the input clock signal lags the phase of the first clock signal, and change the count value in a second direction when the phase of the input clock signal leads the phase of the first clock signal; and
a digital to analog converter circuit to generate an analog control signal from the count value, wherein the analog control signal steers the phase of the first clock signal between the respective phases of each clock signal of the pair of clock signals.
60. A synchronous memory device comprising:
an array of memory cells to store data;
clock synchronization circuitry including:
a plurality of delay stages coupled in series;
a first multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a first internal clock signal, the selection being controlled by a first plurality of control signals;
a first shift register circuit to generate the first plurality of control signals in accordance with information indicative of whether a phase of an external clock signal leads or lags a phase of an internal transmit clock signal; and
a detector circuit to compare the phase of the external clock signal with the phase of the internal transmit clock signal and generate the information; and
interface circuitry to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using the first internal clock signal.
61. The memory device of claim 60 further comprising:
a second multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a second internal clock signal, the selection being controlled by a second plurality of control signals; and
a second shift register circuit to generate the second plurality of control signals in accordance with the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.
62. The memory device of claim 61 further comprising:
interpolator circuitry to generate the internal transmit clock signal by interpolating between phases of the first and a second internal clock signals in accordance with a control voltage; and
a control circuit to generate the control voltage according to the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.
63. The memory device of claim 62 wherein the control circuit comprises:
a counter circuit to generate a digital count value based on the information; and
a digital to analog converter to generate the control voltage based on the digital count value.
64. The memory device of claim 60 , wherein the first internal clock signal is generated by an output of a delay stage of the plurality of delay stages.
65. The memory device of claim 60 wherein the plurality of delay stages is included in a phase locked loop circuit.
66. A synchronous memory device comprising:
an array of memory cells to store data;
a plurality of delay elements coupled in series, each delay element generating a respective output signal having a different phase;
a detector circuit to compare a phase of an external clock signal with a phase of an internal transmit clock signal, the detector circuit to generate information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal;
a multiplexer circuit, coupled to the plurality of delay elements, to select a first output signal generated by the plurality of delay elements in response to the information; and
an interface circuit to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using at least the first output signal selected by the multiplexer circuit.
67. The memory device of claim 66 further comprising a shift register coupled to the multiplexer circuit to control selection of the first output signal.
68. The memory device of claim 66 further comprising:
a control circuit to generate a control voltage that is responsive to the information; and
interpolator circuitry to generate the internal transmit clock signal using the first output signal and a second output signal generated by the plurality of delay elements, the phase of the internal transmit clock signal being interpolated between the phases of the first and second output signals in response to the control voltage.
69. The memory device of claim 68 wherein the control circuit comprises:
a digital converter to generate a digital count value in response to the information; and
a digital to analog converter to generate the control voltage using the digital count value.
70. The memory device of claim 66 wherein the plurality of delay elements is included in a phase locked loop circuit.
71. A clock synchronization circuit comprising:
a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a respective delay time with respect to a reference clock signal; and
interpolator circuitry coupled to the plurality of delay stages, the interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether the phase of the first clock signal leads or lags a target phase, wherein the target phase is based on transitions in an input signal.
72. The clock synchronization circuit of claim 71 further comprising detector circuitry coupled to the interpolator circuitry, the detector circuitry to compare the phase of the first clock signal with the target phase, the detector circuitry to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase.
73. The clock synchronization circuit of claim 72 wherein the detector circuitry comprises a counter circuit to change a count value in a first direction when the target phase lags the phase of the first clock signal, and change the count value in a second direction when the target phase leads the phase of the first clock signal, wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is based on the count value.
74. The clock synchronization circuit of claim 73 wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is provided as an analog control signal, and wherein the detector circuitry further comprises a digital to analog converter circuit coupled to the counter circuit, the digital to analog converter circuit to generate the analog control signal from the count value, wherein the analog control signal controls interpolation between the respective phases of the clock signals of the pair of clock signals to produce the phase of the first clock signal.
75. The clock synchronization circuit of claim 71 wherein the target phase is detected based on sampling of the input signal.
76. The clock synchronization circuit of claim 75 wherein the input signal is sampled using the first clock signal.
77. The clock synchronization circuit of claim 76 wherein the input signal is a clock signal.
78. The clock synchronization circuit of claim 71 wherein the input signal includes clock information.
79. The clock synchronization circuit of claim 78 wherein the input signal is a clock signal.
80. The clock synchronization circuit of claim 79 wherein the input signal and the reference clock signal are both derived from an external clock signal.
81. The clock synchronization circuit of claim 80 wherein the input signal is the reference clock signal.
82. The clock synchronization circuit of claim 71 wherein the plurality of delay stages is an even number of delay stages.
83. The clock synchronization circuit of claim 71 wherein the plurality of delay stages and the interpolator circuitry are formed on a single integrated circuit device.
84. The clock synchronization circuit of claim 83 further comprising a buffer coupled to the interpolator circuitry, the buffer to receive the input signal from external to the integrated circuit device.
85. The clock synchronization circuit of claim 83 further comprising a buffer coupled to the plurality of delay stages, the buffer to receive the reference clock signal from external to the integrated circuit device.
86. The clock synchronization circuit of claim 71 wherein each delay stage of the plurality of delay stages comprises:
a first output terminal;
a second output terminal;
a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and
a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.
87. The clock synchronization circuit of claim 71 wherein the plurality of delay stages is included in a phase locked loop circuit.
88. The clock synchronization circuit of claim 71 further comprising selection circuitry coupled to the interpolator circuitry, the selection circuitry to select the pair of clock signals from the plurality of clock signals.
89. The clock synchronization circuit of claim 71 further comprising a phase detector to compare the phase of the first clock signal with the target phase, and to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase, wherein the information is represented by a binary signal.
90. The clock synchronization circuit of claim 71 wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.
91. A method for clock synchronization, comprising:
generating a plurality of clock signals from a reference clock signal, wherein each clock signal of the plurality of clock signals is delayed from the reference clock signal by a corresponding delay time such that a plurality of different delays with respect to the reference clock signal are represented in the plurality of clock signals;
detecting phase of an input signal, wherein the phase of the input signal represents a target phase; and
generating a first clock signal based on a pair of clock signals of the plurality of clock signals, wherein generating the first clock signal includes interpolation between the pair of clock signals using information indicative of whether the phase of the first clock signal leads or lags the target phase.
92. The method of claim 91 wherein detecting phase of the input signal further comprises sampling the input signal.
93. The method of claim 92 wherein sampling the input signal further comprises sampling the input signal based on the first clock signal.
94. The method of claim 93 wherein the input signal is a clock signal.
95. The method of claim 94 wherein the input signal and the reference clock signal are generated from an external clock signal.
96. The method of claim 92 further comprises selecting the pair of clock signals from the plurality of clock signals based on the sampling of the input signal.
97. The method of claim 91 wherein generating the plurality of clock signals further comprises generating the plurality of clock signals using a plurality of delay stages coupled in series, wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.
98. The method of claim 91 wherein the input signal includes clock information.
99. The method of claim 98 wherein the input signal is a clock signal.
100. An integrated circuit comprising:
a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage of the plurality of delay stages having a delay time with respect to a reference clock signal;
a phase detector to determine the phase of an input signal by sampling the input signal, wherein the phase of the input signal is based on at least one transition in the input signal, the phase detector to generate information indicative of whether a phase of a first clock signal leads or lags the phase of the input signal; and
interpolator circuitry coupled to the plurality of delay stages and the phase detector, the interpolator circuitry to generate the first clock signal using a pair of clock signals of the plurality of clock signals, wherein the phase of the first clock signal is interpolated between respective phases of the pair of clock signals in accordance with the information indicative of whether the phase of the first clock signal leads or lags the phase of the input signal.
101. The integrated circuit of claim 100 wherein the phase detector samples the input signal using the first clock signal.
102. The integrated circuit of claim 100 wherein the input signal includes clock information.
103. The integrated circuit of claim 102 wherein the input signal is a clock signal.Cited by (0)
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