Inventor

CHEN HSI-CHUAN

TW27 patents

⚠️ This page may combine multiple inventors who share the name “CHEN HSI-CHUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN HSI-CHUAN

VANGUARD INT SEMICONDUCT CORP

Process to reduce defect formation occurring during shallow trench isolation formation

Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications

Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure

Process for recess-free planarization of shallow trench isolation

One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications

Method for fabricating a stacked, or crown shaped, capacitor structure

Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure

Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion

Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures

Locos method with double polysilicon/silicon nitride spacer

Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer

In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application

In-situ nitride and oxynitride deposition process in the same chamber

WINBOND ELECTRONICS CORP

Lading plug contact pattern for DRAM application

Method of fabricating deep trench capacitor

Method of manufacturing DRAM capacitor

Low leakage and low resistance for memory and the manufacturing method for the plugs

SILICON PERSPECTIVE CORP

Design hierarchy-based placement

Method for generating a partitioned IC layout

CADENCE DESIGN SYSTEMS INC

Scalable, partitioning integrated circuit layout system

Trial placement system with cloning

SPRINGSOFT USA INC

Optimizing a circuit design

Timing of a circuit design

WINDBOND ELECTRONICS CORP

Method of fabricating a self-aligned contact opening

TYTON BIOSCIENCES LLC

Nicotine resistant microorganisms

ORCHID GENE LLC

Porous ceramic member with nano silver coating for filtering a plant growth medium and method of application

CHEN HSI-CHUAN

Real-time insulation detector for feeding high-frequency low-voltage signal of power system