Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer

Abstract

A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG silicon layer, on a doped amorphous silicon, storage node shape, with the HSG silicon layer supplying increased surface area, and thus increased capacitance, for the DRAM capacitor. A doped polysilicon layer, selectively deposited on the underlying HSG silicon layer, supplies additional dopant to the HSG silicon layer, residing on the doped amorphous silicon, storage node shape, thus minimizing a capacitance depletion phenomena, that can be present with lightly doped storage node structures.

What is claimed is: 
     
       1. A method of fabricating a capacitor structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprising the steps of: providing an underlying transfer gate transistor, comprised of a gate structure, on a gate insulator layer, insulator spacers on the sides of said gate structure, and a source/drain region in an area of said semiconductor substrate, not covered by said gate structure;   forming a storage node contact hole, in a composite insulator layer, exposing the top surface of a source region;   forming a doped polysilicon plug, in said storage node contact hole;   forming an opening in a thick insulator layer, exposing a portion of the top surface of said composite insulator layer, and exposing the top surface of said doped polysilicon plug;   depositing a doped amorphous silicon layer;   removing said doped amorphous silicon layer from the top surface of said thick insulator layer, creating an amorphous silicon, storage node shape, in said opening, in said insulator layer;   removing said thick insulator layer, resulting in the formation of a crown shaped, amorphous silicon, storage node shape, comprised of vertical shaped of said doped amorphous silicon layer, with said vertical shapes of said doped amorphous silicon layer, connected to a horizontal shape, of said doped amorphous silicon layer, and with said horizontal shape of said doped amorphous silicon layer, overlying and contacting, said doped polysilicon plug;   performing a pre-clean procedure, to remove native oxide from the exposed surfaces of said doped amorphous silicon layer, of said crown shaped, amorphous silicon, storage node shape;   selectively forming hemispherical grain, (HSG), silicon seeds, on the surfaces of said doped amorphous silicon layer, of said crown shaped, amorphous silicon, storage node shape;   annealing to convert said HSG silicon seeds, to a HSG silicon layer, resulting in a crown shaped, storage node electrode, comprised of said HSG silicon layer, on said crown shaped, amorphous silicon, storage node shape;   selectively depositing a doped polysilicon layer, on said HSG silicon layer, of said crown shaped, storage node electrode;   forming a capacitor dielectric layer on said doped polysilicon, of said crown shaped, storage node electrode, resulting in dopant from said doped polysilicon layer, diffusing into said HSG silicon layer, during the formation of said capacitor dielectric layer; and   forming an upper plate electrode, for said capacitor structure.   
     
     
       2. The method of claim 1, wherein said doped polysilicon plug is formed from a polysilicon layer, obtained using LPCVD procedures, to a thickness between about 1000 to 6000 Angstroms, and in situ doped during deposition, via the addition of phosphine or arsine, to a silane ambient, resulting in a bulk concentration for said doped polysilicon plug between about 1E19 to 2E20 atoms/cm 3 . 
     
     
       3. The method of claim 1, wherein said thick insulator layer is a silicon oxide layer, obtained via LPCVD or PECVD procedures, to a thickness between about 4000 to 20000 Angstroms. 
     
     
       4. The method of claim 1, wherein said thick insulator layer is a boro-phosphosilicate glass, (BPSG), layer, deposited using LPCVD or PECVD procedures, to a thickness between about 4000 to 20000 Angstroms. 
     
     
       5. The method of claim 1, wherein said opening, in said insulator layer, is formed via an anisotropic RIE procedure, using CHF 3  as an etchant. 
     
     
       6. The method of claim 1, wherein said doped amorphous silicon layer is obtained using LPCVD procedures, at a temperature below 550° C., to a thickness between about 300 to 2000 Angstroms, and doped in situ, during deposition, via the addition of phosphine, to a silane, or to a disilane ambient, resulting in a bulk concentration below 6E20 atoms/cm 3 . 
     
     
       7. The method of claim 1, wherein said HSG silicon seeds are selectively formed on said doped amorphous silicon layer, of said crown shaped, amorphous silicon, storage node shape, at a temperature between about 500 to 800° C., at a pressure less than 1 torr, using silane, or disilane, in a helium ambient. 
     
     
       8. The method of claim 1, wherein said HSG silicon layer is formed, from said HSG silicon seeds, via said annealing, performed at a temperature between about 500 to 800° C., at a pressure below 1 torr, in a nitrogen ambient. 
     
     
       9. The method of claim 1, wherein said doped polysilicon layer is selectively deposited on said HSG silicon layer, at a temperature between about 500 to 800° C., to a thickness below 100 Angstroms, and doped in situ, during deposition, via the addition of phosphine, or arsine, to a silane, or to a disilane ambient, resulting in a bulk concentration of about 3E20 atoms/cm 3 . 
     
     
       10. The method of claim 1, wherein said capacitor dielectric layer is ONO, at an equivalent silicon dioxide thickness between about 40 to 80 Angstroms, created by an initial thermal oxidation to form a silicon oxide layer, at a thickness between about 10 to 50 Angstroms, followed by a deposition of silicon nitride, to a thickness between about 10 to 60 Angstroms, and thermal oxidation of said silicon nitride layer, at a temperature between about 700 to 1000° C., creating a silicon oxynitride layer, on the underlying, said silicon oxide layer, and driving dopant from said doped polysilicon layer, into said HSG silicon layer. 
     
     
       11. A method of fabricating a crown shaped, storage node electrode, for a DRAM capacitor structure, on a semiconductor substrate, featuring an HSG silicon layer, used to increase the surface area of the crown shaped, storage node electrode, and featuring a doped polysilicon layer, selectively deposited on said HSG silicon layer, used to dope the underlying HSG silicon layer, comprising the steps of: providing an underlying transfer gate transistor, on said semiconductor substrate, comprised of a polysilicon gate structure, with insulator spacers on the sides of said polysilicon gate structure, overlying a silicon dioxide gate insulator layer, and a source/drain region, in an area of said semiconductor substrate, not covered by said gate structure;   depositing a composite insulator layer, comprised of an underlying silicon oxide layer, and an overlying silicon nitride layer;   forming a storage node contact hole in said composite insulator layer, exposing the top surface of the source region, of said source/drain region;   depositing a first doped polysilicon layer, completely filling said storage node contact hole;   removing said first doped polysilicon layer, from the top surface of said composite insulator layer, forming a doped polysilicon plug, in said storage node contact hole;   depositing a thick insulator layer;   forming an opening in said thick insulator layer, exposing the top surface of said doped polysilicon plug, and exposing a portion of the top surface of the silicon nitride layer, used as the overlying layer of said composite insulator layer;   depositing a doped amorphous silicon layer;   removing said doped amorphous silicon layer, from the top surface of said thick insulator layer, creating a doped, amorphous silicon, storage node shape;   removing said thick insulator layer from top surface of said composite insulator layer, resulting in a crown shaped, doped amorphous silicon, storage node shape, comprised of two doped amorphous silicon vertical shapes, connected by a doped amorphous silicon horizontal shape, with said doped amorphous silicon horizontal shape overlying and contacting said doped polysilicon plug structure;   performing a dilute hydrofluoric, (DHF), acid, pre-clean procedure, to remove native oxide from the surface of said crown shaped, doped amorphous silicon, storage node shape;   selectively depositing HSG silicon seeds, in said UHV system, on the exposed surfaces of said doped amorphous silicon layer, of said crown shaped, doped amorphous silicon, storage node shape;   performing an anneal, in situ, in said UHV system, to convert said HSG silicon seeds, to said HSG silicon layer, resulting in the formation of said crown shaped, storage node electrode, comprised of said HSG silicon layer, on said crown shaped, doped amorphous silicon, storage node shape;   selectively depositing a second heavily doped polysilicon layer, on the HSG silicon layer of said crown shaped, storage node electrode, in situ, in said UHV system;   forming a capacitor dielectric layer on said crown shaped storage node electrode, resulting in dopant from said second heavily doped polysilicon layer, diffusing into said HSG silicon layer, during the procedure used to form said capacitor dielectric layer; depositing a polysilicon layer; and   patterning of said polysilicon layer to form a polysilicon upper electrode, for said DRAM capacitor structure.   
     
     
       12. The method of claim 11, wherein said composite insulator layer is comprised of an underlying layer of either silicon oxide, or boro-phosphosilicate glass, obtained via LPCVD or PECVD procedures, at a thickness between about 1000 to 5000 Angstroms, and is comprised of an overlying layer of silicon nitride, obtained via LPCVD or PECVD procedures, to a thickness between about 50 to 10000 Angstroms. 
     
     
       13. The method of claim 11, wherein said first doped polysilicon layer, used for said doped polysilicon plug, is obtained using LPCVD procedures, to a thickness between about 1000 to 6000 Angstroms, and doped in situ, during deposition, via the addition of arsine or phosphine, to a silane ambient, resulting in a bulk concentration between, of said doped polysilicon layer, between about 1E19 to 2E20 atoms/cm 3 . 
     
     
       14. The method of claim 11, wherein said doped amorphous silicon layer is deposited using LPCVD procedures, at a temperature below 550° C., to a thickness between about 300 to 2000 Angstroms, and doped in situ, during deposition, via the addition of phosphine to a silane, or to a disilane ambient, resulting in a bulk concentration below about 6E20 atoms/cm 3 . 
     
     
       15. The method of claim 11, wherein said DHF acid pre-clean procedure, is performed to remove native oxide from the surface of said doped amorphous silicon layer. 
     
     
       16. The method of claim 11, wherein said HSG silicon seeds are selectively formed, in said UHV system, at a temperature between about 500 to 800° C., at a pressure less than 1.0 torr, using silane, or disilane, or using silane, or disilane, in a helium ambient. 
     
     
       17. The method of claim 11, wherein said HSG silicon layer is formed from said HSG silicon seeds, via said anneal, performed in situ, in said UHV system, at a temperature between about 500 to 800° C., at a pressure below 1 torr. 
     
     
       18. The method of claim 11 wherein said second heavily doped polysilicon layer is selectively deposited, on said HSG silicon layer, in situ, in said UHV system, at a temperature between about 500 to 800° C., to a thickness below 100 Angstroms, and doped in situ, during deposition, via the addition of arsine, or phosphine, to a silane, or to a disilane ambient, resulting in a bulk concentration of about 3E20 atoms/cm 3 .