Inventor

CASEY JON A

US62 patents

⚠️ This page may combine multiple inventors who share the name “CASEY JON A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CASEY JON A

IBM

Method of forming a multilayer electronic packaging substrate with integral cooling channels

Thermoelectric devices and methods for making the same

Thermoelectric devices and methods for making the same

Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof

Method of making multilayered ceramic structures having an internal distribution of copper-based conductors

Large ceramic article and method of manufacturing

Low-K dielectric material system for IC application

Low-k dielectric material system for IC application

Powdered metallic sheet method for deposition of substrate conductors

Thermoelectric devices and methods for making the same

Process for via fill

Ceramic via composition, multilayer ceramic circuit containing same, and process for using same

Low dielectric composite substrate

System for cleaning residual paste from a mask

Optimized in-line mask cleaning system

Method for making ceramic substrates from thin and thick ceramic greensheets

Process for fabricating a low dielectric composite substrate

Tracking thermal mini-cycle stress

Method and apparatus for filling vias

Process for fabricating a low dielectric composite substrate

Low dielectric composite substrate

Controlled porosity for ceramic contact sheets and setter tiles

Under die surface mounted electrical elements

Method for integrating thermistor

Process for screening features on an electronic substrate with a low viscosity paste

Ceramic via composition, multilayer ceramic circuit containing same, and process for using same

Toughened glass ceramic substrates for semiconductor devices subjected to oxidizing atmospheres during sintering

Ceramic composite body

Method of making an interface layer for stacked lamination sizing and sintering

Method of making an interface layer for stacked lamination sizing and sintering

Aluminum nitride body having graded metallurgy

Aluminum nitride body having graded metallurgy

Phenyl-endcapped depolymerizable polymer

Direct bonded heterogeneous integration packaging structures

Low temperature sintering of ferrite materials

Phenyl-endcapped depolymerizable polymer

Multi-level web structure in use for thin sheet processing

Suspension for filling via holes in silicon and method for making the same

Polygon integrated circuit (IC) packaging

Materials and method to seal vias in silicon substrates

Apparatus and insertless method for forming cavity substrates using coated membrane

Electronic device console with natural draft cooling

Direct bonded heterogeneous integration packaging structures

Method of using an interface layer for stacked lamination sizing and sintering

Electronic package repair process

Method of selective plating on a substrate

CASEY JON A

Achieving mechanical and thermal stability in a multi-chip package

Achieving mechanical and thermal stability in a multi-chip package

Enhanced thermal management for improved module reliability

BODENWEBER PAUL F

Electronic device console with natural draft cooling