Direct bonded heterogeneous integration packaging structures

Abstract

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

What is claimed is: 
     
       1. An integrated circuit packaging structure free of an interposer layer, the integrated circuit packaging structure comprising:
 a packaging substrate comprising first and second opposing surfaces, and a trench provided in the first opposing surface, wherein the first opposing surface defining the trench is free of electrical connections; 
 a bridge disposed in the trench; and 
 at least two chips in a side by side arrangement overlying the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement, the at least two chips comprising a plurality of electric connections coupled to corresponding electrical connections on the bridge and on the packaging substrate, wherein each of the at least two chips are supported completely by the corresponding electrical connections and an underfill material. 
 
     
     
       2. The integrated circuit packaging structure of  claim 1 , further comprising a lid and a thermal interface material overlaying the chips. 
     
     
       3. The integrated circuit packaging structure of  claim 1 , further comprising an underfill material between the plurality of electrical connections coupled to the corresponding electrical connections on the bridge and the packaging substrate. 
     
     
       4. The integrated circuit packaging structure of  claim 1 , wherein the bridge comprises a chip. 
     
     
       5. The integrated circuit packaging structure of  claim 1 , wherein the bridge comprises wiring effective to provide electrical communication between the at least two chips in the side by side arrangement. 
     
     
       6. The integrated circuit packaging structure of  claim 1 , wherein the bridge comprises a memory chip or a microprocessor chip and the at least two chips in the side by side relationship comprise a microprocessor chip and a power supply chip. 
     
     
       7. The integrated circuit packaging structure of  claim 1 , wherein the packaging substrate comprises a laminate of multiple layers. 
     
     
       8. The integrated circuit packaging structure of  claim 1 , wherein the plurality of electrical connections on the least two chips and the corresponding electrical connections on the bridge and on the packaging substrate comprise a solder bump, a solder ball, a conductive stud, a conductive via, a conductive pillar, or combinations thereof. 
     
     
       9. The integrated circuit packaging structure of  claim 1 , wherein the at least two chips in a side by side arrangement comprise molded known good chips. 
     
     
       10. The integrated circuit packaging structure of  claim 1 , wherein the at least two chips in a side by side arrangement comprise multiple chips diced from a wafer as a group. 
     
     
       11. An integrated circuit packaging structure free of an interposer layer, the integrated circuit packaging structure comprising:
 a packaging substrate comprising first and second opposing surfaces, a pedestal provided in the first surface; 
 at least one bridge having one end disposed adjacent to the pedestal; and 
 at least two chips in a side by side arrangement overlying the at least one bridge and the packaging substrate, wherein the at least one bridge underlies peripheral edges of the at least two chips in the side by side arrangement, the at least two chips comprising a plurality of electric connections coupled to corresponding electrical connections on the bridge and on the packaging substrate, wherein the corresponding electrical connections on the packaging substrate are adjacent to another end of the bridge and on the pedestal, wherein the corresponding electrical connections adjacent to the other end of the bridge are larger than the corresponding electrical connections on the pedestal. 
 
     
     
       12. The integrated circuit packaging structure of  claim 11 , wherein the at least one bridge comprises a chip. 
     
     
       13. The integrated circuit packaging structure of  claim 11 , wherein the at least one bridge comprises wiring effective to provide electrical communication between the at least two chips in the side by side arrangement. 
     
     
       14. The integrated circuit packaging structure of  claim 11 , wherein the at least one bridge is a high bandwidth memory chip and the at least two chips in the side by side proximal arrangement comprise a microprocessor chip and a power supply chip. 
     
     
       15. The integrated circuit packaging structure of  claim 11 , wherein the plurality of electrical connections on the least two chips are coupled to corresponding electrical connections on the at least one bridge and on the packaging substrate comprise a solder bump, a solder ball, a conductive stud, a conductive via, a conductive pillar, or combinations thereof.