P

Inventor

SOLTIS JR DONALD CHARLES

US24 patents
⚠️ This page may combine multiple inventors who share the name “SOLTIS JR DONALD CHARLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEWLETT PACKARD DEVELOPMENT CO

20 patents
US6721875B1Apr 13, 2004

Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form

HEWLETT PACKARD DEVELOPMENT CO84 citations97
US7343479B2Mar 11, 2008

Method and apparatus for implementing two architectures in a chip

HEWLETT PACKARD DEVELOPMENT CO18 citations92
US6715060B1Mar 30, 2004

Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data

HEWLETT PACKARD DEVELOPMENT CO21 citations92
US6711670B1Mar 23, 2004

System and method for detecting data hazards within an instruction group of a compiled computer program

HEWLETT PACKARD DEVELOPMENT CO21 citations92
US6591393B1Jul 8, 2003

Masking error detection/correction latency in multilevel cache transfers

HEWLETT PACKARD DEVELOPMENT CO17 citations92
US7237144B2Jun 26, 2007

Off-chip lockstep checking

HEWLETT PACKARD DEVELOPMENT CO43 citations91
US7287185B2Oct 23, 2007

Architectural support for selective use of high-reliability mode in a computer system

HEWLETT PACKARD DEVELOPMENT CO18 citations84
US6711671B1Mar 23, 2004

Non-speculative instruction fetch in speculative processing

HEWLETT PACKARD DEVELOPMENT CO14 citations84
US6651164B1Nov 18, 2003

System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error

HEWLETT PACKARD DEVELOPMENT CO18 citations84
US6587940B1Jul 1, 2003

Local stall/hazard detect in superscalar, pipelined microprocessor to avoid re-read of register file

HEWLETT PACKARD DEVELOPMENT CO16 citations84
US7281147B2Oct 9, 2007

Systems and methods for variable control of power dissipation in a pipelined processor

HEWLETT PACKARD DEVELOPMENT CO9 citations74
US6643762B1Nov 4, 2003

Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs

HEWLETT PACKARD DEVELOPMENT CO8 citations73
US6618801B1Sep 9, 2003

Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information

HEWLETT PACKARD DEVELOPMENT CO10 citations73
US6604192B1Aug 5, 2003

System and method for utilizing instruction attributes to detect data hazards

HEWLETT PACKARD DEVELOPMENT CO9 citations73
US6622238B1Sep 16, 2003

System and method for providing predicate data

HEWLETT PACKARD DEVELOPMENT CO12 citations72
US6874116B2Mar 29, 2005

Masking error detection/correction latency in multilevel cache transfers

HEWLETT PACKARD DEVELOPMENT CO4 citations62
US7243215B2Jul 10, 2007

System and method for utilizing a scoreboard to indicate information pertaining to pending register writes

HEWLETT PACKARD DEVELOPMENT CO0 citations52
US7146490B2Dec 5, 2006

Processing system and method for efficiently enabling detection of data hazards for long latency instructions

HEWLETT PACKARD DEVELOPMENT CO1 citations52
US6728868B2Apr 27, 2004

System and method for coalescing data utilized to detect data hazards

HEWLETT PACKARD DEVELOPMENT CO1 citations52
US7213132B2May 1, 2007

System and method for providing predicate data to multiple pipeline stages

HEWLETT PACKARD DEVELOPMENT CO1 citations50

HEWLETT PACKARD CO

3 patents

HEWLETT PACKARD COMPANY L P

1 patent