Inventor

SCHUEGRAF KLAUS F

US57 patents

⚠️ This page may combine multiple inventors who share the name “SCHUEGRAF KLAUS F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHUEGRAF KLAUS F

MICRON TECHNOLOGY INC

Uniform dielectric film deposition on textured surfaces

Semiconductor processing methods of chemical vapor depositing SiO2 on a substrate

Rugged metal electrodes for metal-insulator-metal capacitors

Method of deposting uniform dielectric film deposition on textured surfaces

Method of forming integrated stacked capacitors with rounded corners

DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films

Method of fabricating a bottom electrode with rounded corners for an integrated memory cell capacitor

Shallow trench isolation using low dielectric constant insulator

Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon

High pressure reoxidation anneal of silicon nitride for reduced thermal budget silicon processing

Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon

Methods of forming capacitors and related integrated circuitry

Rugged metal electrodes for metal-insulator-metal capacitors

DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films

Method and apparatus for improving the structural integrity of stacked capacitors

Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon

One-time programmable element having controlled programmed state resistance

Semiconductor processing methods of chemical vapor depositing SiO2 on a substrate

Method of selective texfturing for patterned polysilicon electrodes

Shallow trench isolation using low dielectric constant insulator

Rugged metal electrodes for metal-insulator-metal capacitors

Methods of forming capacitors and related integrated circuitry

Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon

Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method

Shallow trench isolation using low dielectric constant insulator

Method of monitoring a process of manufacturing a semiconductor wafer including space hemispherical grain polysilicon

NEWPORT FAB LLC

Method for integrating a metastable base into a high-performance HBT and related structure

Method for reducing base to collector capacitance and related structure

Method for fabricating a selective eptaxial HBT emitter

Method for controlling an emitter window opening in an HBT and related structure

CMOS transistor spacers formed in a BiCMOS process

Metastable base in a high-performance HBT

Method for opening a semiconductor region for fabricating an HBT

Method for controlling critical dimension in a polycrystalline silicon emitter and related structure

Method for forming CMOS transistor spacers in a BiCMOS process

Method for improved alignment tolerance in a bipolar transistor

Bipolar transistor with reduced emitter to base capacitance

Method for eliminating collector-base band gap in an HBT

Structure for a selective epitaxial HBT emitter

Method for controlling critical dimension in an HBT emitter and related structure

Method to reduce emitter to base capacitance and related structure

High performance bipolar transistor

Method for fabricating interfacial oxide in a transistor and related structure

Polycrystalline silicon emitter having an accurately controlled critical dimension

Bipolar transistor and related structure

Structure for eliminating collector-base band gap discontinuity in an HBT

Method and system for fabricating a bipolar transistor and related structure

MICRON TECHNOLOLGY INC

Method of forming capacitors and related integrated circuitry

(unassigned)

Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method

NEWPORT FAB

Method for fabricating lateral PNP heterojunction bipolar transistor and related structure