Inventor
NOWKA KEVIN JOHN
US44 patents
⚠️ This page may combine multiple inventors who share the name “NOWKA KEVIN JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
43 patentsUS6221769B1Apr 24, 2001
Method for integrated circuit power and electrical connections via through-wafer interconnects
IBM254 citations99
US6836849B2Dec 28, 2004
Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements
IBM178 citations98
US6598153B1Jul 22, 2003
Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions
IBM64 citations96
US6014763AJan 11, 2000
At-speed scan testing
IBM75 citations96
US6175852B1Jan 16, 2001
High-speed binary adder
IBM24 citations93
US7353007B2Apr 1, 2008
Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices
IBM14 citations92
US7219244B2May 15, 2007
Control circuitry for power gating virtual power supply rails at differing voltage potentials
IBM27 citations92
US6717452B2Apr 6, 2004
Level shifter
IBM26 citations92
US6578063B1Jun 10, 2003
5-to-2 binary adder
IBM26 citations92
US6570408B2May 27, 2003
Charge recovery for dynamic circuits
IBM24 citations92
US6529084B1Mar 4, 2003
Interleaved feedforward VCO and PLL
IBM23 citations92
US6335900B1Jan 1, 2002
Method and apparatus for selectable wordline boosting in a memory device
IBM20 citations92
US7088141B2Aug 8, 2006
Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching
IBM21 citations91
US6650163B1Nov 18, 2003
Clock generator for integrated circuit
IBM25 citations91
US6441667B1Aug 27, 2002
Multiphase clock generator
IBM29 citations90
US7952422B2May 31, 2011
Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices
IBM11 citations84
US7522670B2Apr 21, 2009
Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation
IBM9 citations84
US7336105B2Feb 26, 2008
Dual gate transistor keeper dynamic logic
IBM9 citations84
US6629235B1Sep 30, 2003
Condition code register architecture for supporting multiple execution units
IBM17 citations84
US6282557B1Aug 28, 2001
Low latency fused multiply-adder
IBM19 citations84
US6594679B1Jul 15, 2003
Leading-zero anticipator having an independent sign bit determination module
IBM13 citations82
US6237085B1May 22, 2001
Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation
IBM16 citations82
US6545512B2Apr 8, 2003
Low leakage sleep mode for dynamic circuits
IBM8 citations74
US6529924B1Mar 4, 2003
Method and apparatus for generating shift amount signals for an alignment shifter
IBM9 citations74
US6345286B1Feb 5, 2002
6-to-3 carry-save adder
IBM9 citations74
US6212619B1Apr 3, 2001
System and method for high-speed register renaming by counting
IBM10 citations74
US6178437B1Jan 23, 2001
Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor
IBM10 citations74
US6166437ADec 26, 2000
Silicon on silicon package with precision align macro
IBM12 citations74
US6801025B2Oct 5, 2004
Method and apparatus for control of voltage regulation
IBM10 citations73
US6724221B2Apr 20, 2004
Circuitry having exclusive-OR and latch function, and method therefor
IBM7 citations73
US6445217B1Sep 3, 2002
Edge-triggered latch with balanced pass-transistor logic trigger
IBM7 citations73
US6035390AMar 7, 2000
Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation
IBM15 citations73
US6480049B2Nov 12, 2002
Multiphase clock generator
IBM11 citations71
US7265589B2Sep 4, 2007
Independent gate control logic circuitry
IBM2 citations63
US7142015B2Nov 28, 2006
Fast turn-off circuit for controlling leakage
IBM6 citations63
US6405231B1Jun 11, 2002
Method and apparatus for rounding intermediate normalized mantissas within a floating-point processor
IBM5 citations63
US6335650B1Jan 1, 2002
Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages
IBM5 citations63
US7636556B2Dec 22, 2009
Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices
IBM2 citations62
US6360238B1Mar 19, 2002
Leading zero/one anticipator having an integrated sign selector
IBM6 citations61
US8010066B2Aug 30, 2011
Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices
IBM0 citations52
US7876131B2Jan 25, 2011
Dual gate transistor keeper dynamic logic
IBM0 citations52
US7443195B2Oct 28, 2008
Method of transparently reducing power consumption of a high-speed communication link
IBM0 citations51
US6812739B2Nov 2, 2004
Method of transparently reducing power consumption of a high-speed communication link
IBM0 citations51