Inventor

BOHR MARK

US70 patents

⚠️ This page may combine multiple inventors who share the name “BOHR MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOHR MARK

INTEL CORP

Silicon on insulator (SOI) transistor and methods of fabrication

Transistors with increased mobility in the channel zone and method of fabrication

Designs and methods for conductive bumps

Microcircuit fabrication and interconnection

Self-aligned contacts to gates

Self-aligned gate edge and local interconnect and method to fabricate same

Method of forming abrupt source drain metal gate transistors

Microcircuit fabrication and interconnection

Microcircuit fabrication and interconnection

Selective spacer formation on transistors of different classes on the same device

Self aligned compact bipolar junction transistor layout and method of making same

Super self-aligned collector device for mono-and hetero bipolar junction transistors

Methods of forming electromigration and thermal gradient based fuse structures

Self-aligned gate edge and local interconnect and method to fabricate same

Gate contact structure over active gate and method to fabricate same

Strained silicon MOS device with box layer between the source and drain regions

Forming self-aligned nano-electrodes

Damascene process for fabricating interconnect layers in an integrated circuit

Stepped tip junction with spacer layer

Self-aligned contacts to gates

Concentration graded carbon doped oxide

Integrated circuit structures having asymmetric source and drain structures

Device, method and system for providing a stacked arrangement of integrated circuit dies

Deep trench via for three-dimensional integrated circuit

High density and fine pitch interconnect structures in an electric test apparatus

Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making same

Bipolar junction transistor with improved extrinsic base region and method of fabrication

Device layer interconnects

Device, system and method for providing inductor structures

Gate contact structure over active gate and method to fabricate same

Self-aligned gate edge and local interconnect

Die interconnection scheme for providing a high yielding process for high performance microprocessors

Device, method and system for providing a stacked arrangement of integrated circuit dies

Active region spacer for semiconductor devices and method to form the same

Self-aligned contacts to gates

Integrated circuit having etch-resistant layer substantially covering shallow trench regions

Integrated circuit processing with improved gate electrode fabrication

Device layer interconnects

Gate contact structure over active gate and method to fabricate same

Deep trench via for three-dimensional integrated circuit

Device layer interconnects

Self-aligned gate edge and local interconnect

High density and fine pitch interconnect structures in an electric test apparatus

Designs and methods for conductive bumps

Silicon interposer-based hybrid voltage regulator system for VLSI devices

KUHN KELIN J

Copper-filled trench contact for transistor performance improvement

Copper-filled trench contact for transistor performance improvement

DUBIN VALERY M

Designs and methods for conductive bumps

Designs and methods for conductive bumps

PETHE ABHIJIT JAYANT

Gate contact structure over active gate and method to fabricate same