Die interconnection scheme for providing a high yielding process for high performance microprocessors

Abstract

A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

What is claimed is: 
     
       1. A die, comprising:
 a plurality of semiconductor sections; and 
 an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die, wherein the interconnection structure includes a top layer interconnect structure that connects the plurality of semiconductor sections, and the interconnection structure includes a bridge die, the bridge die on a side of the plurality of semiconductor sections opposite the top layer interconnect structure. 
 
     
     
       2. The die of  claim 1 , wherein the top layer interconnect structure includes stitch wires that connect top layer interconnects that correspond to a first semiconductor section to top layer interconnects that correspond to a second semiconductor section. 
     
     
       3. The die of  claim 1 , wherein the bridge die is connected above first and second semiconductor sections. 
     
     
       4. The die of  claim 1 , wherein the bridge die is connected underneath first and second semiconductor sections. 
     
     
       5. The die of  claim 1 , wherein the bridge die includes interconnect input/output (I/O) logic. 
     
     
       6. The die of  claim 1 , wherein the bridge die includes a plurality of SRAM semiconductor layers. 
     
     
       7. The die of  claim 1 , wherein the plurality of semiconductor sections includes separable quadrants. 
     
     
       8. A package, comprising:
 a package substrate; 
 a die on the package substrate including: 
 a plurality of semiconductor sections; and 
 an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die, wherein the interconnection structure includes a top layer interconnect structure that connects the plurality of semiconductor sections, and the interconnection structure includes a bridge die, the bridge die on a side of the plurality of semiconductor sections opposite the top layer interconnect structure; and 
 a computation die above each of the semiconductor sections. 
 
     
     
       9. The package of  claim 8 , wherein the top layer interconnect structure includes stitch wires that connect top layer interconnects that correspond to a first semiconductor section to top layer interconnects that correspond to a second semiconductor section. 
     
     
       10. The package of  claim 8 , wherein the bridge die is connected above first and second semiconductor sections. 
     
     
       11. The package of  claim 8 , wherein the bridge die is connected underneath first and second semiconductor sections. 
     
     
       12. The package of  claim 8 , wherein the bridge die includes interconnect input/output (I/O) logic. 
     
     
       13. The package of  claim 8 , wherein the bridge die includes a plurality of SRAM semiconductor layers. 
     
     
       14. The package of  claim 8 , wherein the plurality of semiconductor sections includes separable quadrants. 
     
     
       15. A method, comprising:
 forming stitching structures to connect interconnects corresponding to die quadrants of sets of die quadrants on a wafer; 
 
       singulating the wafer into the sets of die quadrants and testing the sets of die quadrants; 
       determining if all of the quadrants of the sets of die quadrants pass testing;
 if all of the quadrants of a set of die quadrants pass testing, harvesting the set of die quadrants on a single semiconductor base; and 
 if all of the quadrants of the set of die quadrants do not pass testing, performing a second singulation and leaving one or more functional die quadrants of the set of die quadrants. 
 
     
     
       16. The method of  claim 15 , further comprising:
 forming one or more bridge die to connect the one or more functional die quadrants to one or more other functional die quadrants. 
 
     
     
       17. The method of  claim 15 , wherein forming the stitching structures include forming stitch wires that connect top layer interconnects that correspond to a first die quadrant to top layer interconnects that correspond to a second die quadrant. 
     
     
       18. The method of  claim 16 , wherein the forming the one or more bridge die includes connecting the bridge die above the one or more functional die quadrants and the one or more other functional die quadrants. 
     
     
       19. The method of  claim 16 , wherein the forming the one or more bridge die includes connecting the bridge die underneath the one or more functional die quadrants and the one or more other functional die quadrants. 
     
     
       20. The method of  claim 16 , wherein forming the one or more bridge die includes forming an interconnect to input/output (I/O) logic.