Inventor · disambiguated record
Swaminathan Sivakumar
Also filed as: SIVAKUMAR SWAMINATHAN · SIVAKUMAR SWAMINATHAN SAM
61 granted patents·16 pending applications·507 citations·filing 1996–2024
98Inventor score
Top patents by PatentIndex Score
77 records- 0198US7632610B2Sub-resolution assist featuresINTEL CORP·Filed 2004·Granted Dec 15, 2009·179 cites·20 claims
- 0297US9716037B2Gate aligned contact and method to fabricate sameGOLONZKA OLEG·Filed 2011·Granted Jul 25, 2017·65 cites·15 claims
- 0396US12342612B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2023·Granted Jun 24, 2025·2 cites·20 claims
- 0496US11862635B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2022·Granted Jan 2, 2024·2 cites·20 claims
- 0594US11056492B1Dense memory arrays utilizing access transistors with back-side contactsINTEL CORP·Filed 2019·Granted Jul 6, 2021·9 cites·18 claims
- 0694US10211088B2Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnectsINTEL CORP·Filed 2015·Granted Feb 19, 2019·11 cites·20 claims
- 0793US10325814B2Patterning of vertical nanowire transistor channel and gate with directed self assemblyINTEL CORP·Filed 2017·Granted Jun 18, 2019·5 cites·10 claims
- 0893US9793159B2Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted Oct 17, 2017·13 cites·18 claims
- 0992US8519462B26F2 DRAM cellWANG YIH·Filed 2011·Granted Aug 27, 2013·20 cites·11 claims
- 1091US11139300B2Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2019·Granted Oct 5, 2021·5 cites·20 claims
- 1191US9054215B2Patterning of vertical nanowire transistor channel and gate with directed self assemblyNYHUS PAUL A·Filed 2012·Granted Jun 9, 2015·9 cites·23 claims
- 1289US11398474B2Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regionsINTEL CORP·Filed 2018·Granted Jul 26, 2022·4 cites·12 claims
- 1389US7820550B2Negative tone double patterning methodINTEL CORP·Filed 2008·Granted Oct 26, 2010·10 cites·22 claims
- 1489US2024282633A1Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2024·Application pending·0 cites
- 1588US6968532B2Multiple exposure technique to pattern tight contact geometriesINTEL CORP·Filed 2003·Granted Nov 22, 2005·39 cites·25 claims
- 1687US12033894B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2023·Granted Jul 9, 2024·0 cites·20 claims
- 1786US12432897B2Cooling approaches for stitched diesINTEL CORP·Filed 2021·Granted Sep 30, 2025·1 cites·22 claims
- 1885US11302790B2Fin shaping using templates and integrated circuit structures resulting therefromINTEL CORP·Filed 2018·Granted Apr 12, 2022·3 cites·22 claims
- 1985US11107786B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2019·Granted Aug 31, 2021·2 cites·20 claims
- 2085US7265431B2Imageable bottom anti-reflective coating for high resolution lithographyINTEL CORP·Filed 2002·Granted Sep 4, 2007·27 cites·7 claims
- 2184US11756829B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 2283US12211925B2Gate-all-around integrated circuit structures having oxide sub-finsINTEL CORP·Filed 2023·Granted Jan 28, 2025·0 cites·17 claims
- 2383US10204830B2Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2017·Granted Feb 12, 2019·3 cites·20 claims
- 2482US11652060B2Die interconnection scheme for providing a high yielding process for high performance microprocessorsINTEL CORP·Filed 2018·Granted May 16, 2023·3 cites·20 claims
- 2582US9431518B2Patterning of vertical nanowire transistor channel and gate with directed self assemblyINTEL CORP·Filed 2016·Granted Aug 30, 2016·2 cites·11 claims
- 2681US2025120152A1Gate-all-around integrated circuit structures having oxide sub-finsINTEL CORP·Filed 2024·Application pending·0 cites
- 2780US2024389300A1Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 2879US7816061B2Lithography masks for improved line-end patterningINTEL CORP·Filed 2007·Granted Oct 19, 2010·5 cites·15 claims
- 2977US12426316B2Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric materialINTEL CORP·Filed 2022·Granted Sep 23, 2025·0 cites·24 claims
- 3077US11495496B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2021·Granted Nov 8, 2022·0 cites·20 claims
- 3176US12278204B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2021·Granted Apr 15, 2025·0 cites·15 claims
- 3274US10910265B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2020·Granted Feb 2, 2021·0 cites·20 claims
- 3374US8860184B2Spacer assisted pitch division lithographySIVAKUMAR SWAMINATHAN·Filed 2011·Granted Oct 14, 2014·4 cites·20 claims
- 3474US7981756B2Common plate capacitor array connections, and processes of making sameINTEL CORP·Filed 2008·Granted Jul 19, 2011·5 cites·22 claims
- 3572US12114479B2Three-dimensional memory arrays with layer selector transistorsINTEL CORP·Filed 2021·Granted Oct 8, 2024·0 cites·20 claims
- 3672US11972979B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2023·Granted Apr 30, 2024·0 cites·22 claims
- 3772US10459338B2Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and pluggingINTEL CORP·Filed 2017·Granted Oct 29, 2019·1 cites·3 claims
- 3872US9269630B2Patterning of vertical nanowire transistor channel and gate with directed self assemblyINTEL CORP·Filed 2015·Granted Feb 23, 2016·1 cites·20 claims
- 3970US11749733B2FIN shaping using templates and integrated circuit structures resulting therefromINTEL CORP·Filed 2022·Granted Sep 5, 2023·0 cites·22 claims
- 4070US9224794B2Embedded memory device having MIM capacitor formed in excavated structureINTEL CORP·Filed 2013·Granted Dec 29, 2015·1 cites·6 claims
- 4169US7358111B2Imageable bottom anti-reflective coating for high resolution lithographyINTEL CORP·Filed 2005·Granted Apr 15, 2008·2 cites·5 claims
- 4268US11715775B2Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structuresINTEL CORP·Filed 2022·Granted Aug 1, 2023·0 cites·20 claims
- 4367US10607884B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2019·Granted Mar 31, 2020·0 cites·20 claims
- 4467US9530688B2Directed self assembly of block copolymers to form vias aligned with interconnectsNYHUS PAUL A·Filed 2015·Granted Dec 27, 2016·1 cites·14 claims
- 4567US5933759AMethod of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applicationsINTEL CORP·Filed 1996·Granted Aug 3, 1999·37 cites·33 claims
- 4667US2023245974A1Die interconnection scheme for providing a high yielding process for high performance microprocessorsINTEL CORP·Filed 2023·Application pending·0 cites
- 4766US8959465B2Techniques for phase tuning for process optimizationNYHUS PAUL A·Filed 2011·Granted Feb 17, 2015·1 cites·23 claims
- 4866US7927959B2Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced therebyINTEL CORP·Filed 2008·Granted Apr 19, 2011·3 cites·15 claims
- 4964US11742410B2Gate-all-around integrated circuit structures having oxide sub-finsINTEL CORP·Filed 2019·Granted Aug 29, 2023·0 cites·10 claims
- 5064US10340185B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2017·Granted Jul 2, 2019·0 cites·20 claims
Showing the top 50 of 77 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →