Die interconnection scheme for providing a high yielding process for high performance microprocessors

Abstract

A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

What is claimed is: 
     
         1 . A die, comprising:
 a plurality of semiconductor sections; and   an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die, wherein the interconnection structure includes a top layer interconnect structure that is discontinuous between adjacent ones of the plurality of semiconductor sections, and the interconnection structure includes a bridge die, the bridge die on a same side of the plurality of semiconductor sections as the top layer interconnect structure.   
     
     
         2 . The die of  claim 1 , wherein the bridge die is attached to the top layer interconnect structure. 
     
     
         3 . The die of  claim 1 , wherein the bridge die includes interconnect input/output (I/O) logic. 
     
     
         4 . The die of  claim 1 , wherein the bridge die includes a plurality of SRAM semiconductor layers. 
     
     
         5 . The die of  claim 1 , wherein the top layer interconnect structure includes stitch wires that connect top layer interconnects. 
     
     
         6 . The die of  claim 1 , wherein the plurality of semiconductor sections includes separable quadrants. 
     
     
         7 . A die, comprising:
 a first base die section and a second base die section; and   an interconnection structure connecting the first base die section and the second base die section, wherein the interconnection structure includes a top layer interconnect structure that is discontinuous between the first base die section and the second base die section, and the interconnection structure includes a bridge die, the bridge die on a same side of the first base die section and the second base die section as the top layer interconnect structure.   
     
     
         8 . The die of  claim 7 , wherein the bridge die is attached to the top layer interconnect structure. 
     
     
         9 . The die of  claim 7 , wherein the bridge die includes interconnect input/output (I/O) logic. 
     
     
         10 . The die of  claim 7 , wherein the bridge die includes a plurality of SRAM semiconductor layers. 
     
     
         11 . The die of  claim 7 , wherein the top layer interconnect structure includes stitch wires that connect top layer interconnects. 
     
     
         12 . A package, comprising:
 a package substrate;   a die on the package substrate including:
 a plurality of semiconductor sections; and 
 an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die, wherein the interconnection structure includes a top layer interconnect structure that is discontinuous between adjacent ones of the plurality of semiconductor sections, and the interconnection structure includes a bridge die, the bridge die on a same side of the plurality of semiconductor sections as the top layer interconnect structure; and 
   a die above each of the plurality of semiconductor sections.   
     
     
         13 . The package of  claim 12 , wherein the bridge die is attached to the top layer interconnect structure. 
     
     
         14 . The package of  claim 12 , wherein the bridge die includes interconnect input/output (I/O) logic. 
     
     
         15 . The package of  claim 12 , wherein the bridge die includes a plurality of SRAM semiconductor layers. 
     
     
         16 . The package of  claim 12 , wherein the top layer interconnect structure includes stitch wires that connect top layer interconnects. 
     
     
         17 . The package of  claim 12 , wherein the plurality of semiconductor sections includes separable quadrants.