Inventor
ZHU JIANBIN
CN30 patents
⚠️ This page may combine multiple inventors who share the name “ZHU JIANBIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AZURENGINE TECH ZHUHAI INC
15 patentsUS11182336B2Nov 23, 2021
Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration
AZURENGINE TECH ZHUHAI INC2 citations84
US10956360B2Mar 23, 2021
Static shared memory access with one piece of input data to be reused for successive execution of one instruction in a reconfigurable parallel processor
AZURENGINE TECH ZHUHAI INC3 citations84
US10776310B2Sep 15, 2020
Reconfigurable parallel processor with a plurality of chained memory ports
AZURENGINE TECH ZHUHAI INC3 citations84
US10776311B2Sep 15, 2020
Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports
AZURENGINE TECH ZHUHAI INC3 citations84
US10776312B2Sep 15, 2020
Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports
AZURENGINE TECH ZHUHAI INC3 citations84
US10733139B2Aug 4, 2020
Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports
AZURENGINE TECH ZHUHAI INC4 citations84
US12346248B2Jul 1, 2025
Private memory mode sequential memory access in multi-threaded computing
AZURENGINE TECH ZHUHAI INC0 citations62
US11971847B2Apr 30, 2024
Reconfigurable parallel processing
AZURENGINE TECH ZHUHAI INC0 citations62
US11226927B2Jan 18, 2022
Reconfigurable parallel processing
AZURENGINE TECH ZHUHAI INC0 citations62
US11182333B2Nov 23, 2021
Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit
AZURENGINE TECH ZHUHAI INC0 citations62
US11182334B2Nov 23, 2021
Shared memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit
AZURENGINE TECH ZHUHAI INC0 citations62
US11182335B2Nov 23, 2021
Circular reconfiguration for reconfigurable parallel processor using a plurality of memory ports coupled to a commonly accessible memory unit
AZURENGINE TECH ZHUHAI INC0 citations62
US11176085B2Nov 16, 2021
Reconfigurable parallel processing with various reconfigurable units to form two or more physical data paths and routing data from one physical data path to a gasket memory to be used in a future physical data path as input
AZURENGINE TECH ZHUHAI INC0 citations62
US12131157B2Oct 29, 2024
Mixed scalar and vector operations in multi-threaded computing
AZURENGINE TECH ZHUHAI INC1 citations60
US12360805B2Jul 15, 2025
Vectorized scalar processor for executing scalar instructions in multi-threaded computing
AZURENGINE TECH ZHUHAI INC0 citations52
LI YUAN
5 patentsUS8930791B2Jan 6, 2015
Early stop method and apparatus for turbo decoding
LI YUAN5 citations73
US8819517B1Aug 26, 2014
Systems and methods for a turbo decoder in a universal mobile telecommunication system (UMTS)
LI YUAN2 citations63
US8918695B2Dec 23, 2014
Methods and apparatus for early stop algorithm of turbo decoding
LI YUAN0 citations52
US8839081B2Sep 16, 2014
Rate matching and de-rate matching on digital signal processors
LI YUAN0 citations51
US8806310B2Aug 12, 2014
Rate matching and de-rate matching on digital signal processors
LI YUAN0 citations51