Methods, systems, and apparatus for tail termination of turbo decoding

Abstract

Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.

The invention claimed is: 
     
       1. A decoder, comprising:
 at least one processor configured to: 
 calculate backward state initial values from an input signal, and 
 store the backward state initial values as a pre-computed backward state metric in a memory, 
 for each of a plurality of decoding iterations, the at least one processor is further configured to calculate a forward state metric and calculate a backward state metric, wherein for each decoding iteration for calculating an initial backward state metric, the processor fetches from the memory, the pre-computed backward state metric. 
 
     
     
       2. The decoder of  claim 1 , wherein each decoding iteration for calculating an initial backward state metric is substantially identical. 
     
     
       3. The decoder of  claim 1 , further comprising a turbo decoder. 
     
     
       4. The decoder of  claim 1 , further comprising a radix-4 decoder. 
     
     
       5. The decoder of  claim 1 , wherein at least one iteration further comprises calculating, by the at least one processor, extrinsic information. 
     
     
       6. A method for iteratively decoding by a decoder system comprising at least one processor, the method comprising:
 calculating backward state initial values from an input signal, 
 storing the backward state initial values as a pre-computed backward state metric in a memory, 
 wherein for each of a plurality decoding iterations the at least one processor is further configured to: 
 calculate a forward state metric; 
 calculate a backward state metric, wherein for each decoding iteration for calculating an initial backward state metric, the at least one processor fetches the pre-computed backward state metric from the memory. 
 
     
     
       7. The method of  claim 6 , wherein each decoding iteration for calculating an initial backward state metric is substantially identical. 
     
     
       8. The method of  claim 6 , the decoder system comprising a turbo decoder. 
     
     
       9. The method of  claim 6 , the decoder system comprising a radix-4 decoder. 
     
     
       10. The method of  claim 6 , wherein at least one of the decoding iterations further comprises calculating, by the at least one processor, extrinsic information. 
     
     
       11. A system, comprising:
 a memory; and 
 a decoder system coupled to the memory, the decoder system comprising a processor configured to:
 calculate backward state initial values from an input signal, and 
 store the backward state initial values as a pre-computed backward state metric in a memory, 
 for each of a plurality decoding iterations calculate a forward state metric and calculate a backward state metric, wherein for each decoding iteration for calculating an initial backward state metric, the processor fetches the pre-computed backward state metric from the memory, 
 
 wherein the same initial state of the backward state metric is pre-computed independent of a decoding iteration. 
 
     
     
       12. The system of  claim 11 , wherein each decoding iteration for calculating an initial backward state metric is substantially identical. 
     
     
       13. The system of  claim 11 , wherein the decoder system comprises a turbo decoder. 
     
     
       14. The system of  claim 11 , wherein the decoder system comprises a radix-4 decoder. 
     
     
       15. The system of  claim 11 , wherein at least one of the decoding iterations comprises calculating, by the at least one processor, extrinsic information.