Inventor

LUICK DAVID A

US54 patents

⚠️ This page may combine multiple inventors who share the name “LUICK DAVID A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUICK DAVID A

IBM

Local and global branch prediction information storage

Processor power and energy management

Moving data in and out of processor units using idle register/storage functional units

Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor

Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

Adaptive memory compression

VLIW architecture and method for expanding a parcel

System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline

Simple load and store disambiguation and scheduling at predecode

Simple load and store disambiguation and scheduling at predecode

Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table

Local and global branch prediction information storage

Floating point unit power reduction via inhibiting register file write during tight loop execution

Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code

System for interfacing between main store memory and a central processor

System and method for optimization within a group priority issue schema for a cascaded pipeline

System and method for prioritizing arithmetic instructions

System and method for prioritizing branch instructions

System and method for prioritizing store instructions

Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline

D-cache miss prediction and scheduling

Multiple parallel pipeline processor having self-repairing capability

Runtime repairable processor

Automatic temporary precision reduction for enhanced compression

Methods and arrangements for repairing ports

Method and system for reducing power consumption in a computing device when the computing device executes instructions in a tight loop

Effectively infinite branch prediction table mechanism

Floating point unit power reduction scheme

Icache-based value prediction mechanism

Cache updating in multiprocessor systems

Extended control word decoding

Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code

Self prefetching L3/L4 cache mechanism

3-dimensional L2/L3 cache array to hide translation (TLB) delays

Adaptive thread ID cache mechanism for autonomic performance tuning

Power reduction mechanism for floating point register file reads

System for allowing only a partial value prediction field/cache size

Dual array read port functionality from a one port SRAM

Directoryless L0 cache for stall reduction

Multiport execution target delay queue FIFO array

LUICK DAVID A

Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

Cascaded delayed float/vector execution pipeline

Cache line use history based done bit modification to D-cache replacement scheme

Cache line use history based done bit modification to I-cache replacement scheme

D-cache line use history based done bit based on successful prefetchable counter

Predicated issue for conditional branch instructions

I-cache line use history based done bit based on successful prefetchable counter

Vector morphing mechanism for multiple processor cores

System and method for optimization within a group priority issue schema for a cascaded pipeline

Cache line use history based done bit modification to D-cache replacement scheme