Self prefetching L3/L4 cache mechanism

Abstract

Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effective address may be retrieved relatively quickly from the LLB, thereby allowing access to the cache before the complete address translation is available and reducing cache access latency.

1. A method for retrieving data from memory, comprising:
 receiving an effective address; 
 transmitting the effective address to a translation look-aside buffer (TLB) to retrieve a real address associated with the effective address; 
 using a first set of effective address bits as an index to a look-aside-look-aside buffer (LLB) to retrieve a first set of real address bits, wherein the LLB is configured to store a subset of address translations contained in the TLB; 
 using the first set of real address bits and a second set of effective address bits to access the memory; and 
 completing memory access using the real address retrieved from the TLB. 
 
     
     
       2. The method of  claim 1 , wherein the TLB is a Dynamic Random Access Memory (DRAM). 
     
     
       3. The method of  claim 1 , wherein the LLB is a Static Random Access Memory (SRAM). 
     
     
       4. The method of  claim 1 , wherein the memory is one of a level 3 cache and level 4 cache. 
     
     
       5. The method of  claim 1 , further comprising using a third set of the effective address bits to access a row in the memory. 
     
     
       6. The method of  claim 1 , wherein using the first set of real address bits and a second set of effective address bits to access the memory further comprises using the second set of effective address bits to assert a Row Access Strobe (RAS) signal. 
     
     
       7. The method of  claim 1 , wherein using the first set of real address bits and a second set of effective address bits to access the memory further comprises using the first set of real address bits to assert a Column Access Strobe (CAS) signal. 
     
     
       8. A system comprising: at least one processor core; at least one memory device; a buffer; and access circuitry configured to:
 receive an effective address from the at least one processor core; 
 transmit the effective address to a Translation Look-aside Buffer (TLB) to retrieve a real address associated with the effective address; 
 use a first set of effective address bits as an index to the buffer to retrieve a first set of real address bits, wherein the buffer is configured to store a subset of address translations contained in the TLB; 
 use the first set of real address bits and a second set of effective address bits to access the memory device; and 
 complete access to the memory device using the real address retrieved from the TLB. 
 
     
     
       9. The system of  claim 8 , wherein the memory device is one of a level 3 cache and level 4 cache. 
     
     
       10. The system of  claim 8 , wherein the access circuitry is further configured to use a third set of effective address bits to select a row in the memory device. 
     
     
       11. The system of  claim 8 , wherein using the first set of real address bits and a second set of effective address bits to access the memory further comprises using the second set of effective address bits to assert a Row Access Strobe (RAS) signal. 
     
     
       12. The system of  claim 8 , wherein using the first set of real address bits and a second set of effective address bits to access the memory further comprises using the first set of real address bits to assert a Column Access Strobe (CAS) signal. 
     
     
       13. A processor comprising: a cache; a translation look-aside buffer (TLB); a look-aside-look-aside buffer (LLB); and access circuitry configured to:
 receive an effective address; 
 transmit the effective address to the (TLB) to retrieve a real address associated with the effective address; 
 use a first set of effective address bits as an index to the LLB to retrieve a first set of real address bits, wherein the LLB is configured to store a subset of address translations contained in the TLB; 
 use the first set of real address bits and a second set of effective address bits to initiate access to the cache; and 
 complete cache access using the real address retrieved from the TLB. 
 
     
     
       14. The processor of  claim 13 , wherein the LLB is a Static Random Access Memory (SRAM). 
     
     
       15. The processor of  claim 13 , wherein the access circuitry is further configured to use a third set of effective address bits to select a row in the memory device. 
     
     
       16. The processor of  claim 15 , wherein the access circuitry is configured to use the first set of real address bits to select a column in the memory device. 
     
     
       17. The processor of  claim 13 , wherein using the first set of real address bits and a second set of effective address bits to access the memory further comprises using the second set of effective address bits to assert a Row Access Strobe (RAS) signal. 
     
     
       18. The processor of  claim 13 , wherein using the first set of real address bits and a second set of effective address bits to access the memory further comprises using the first set of real address bits to assert a Column Access Strobe (CAS) signal.