Inventor

MEHROTRA MANOJ

US55 patents

⚠️ This page may combine multiple inventors who share the name “MEHROTRA MANOJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEHROTRA MANOJ

TEXAS INSTRUMENTS INC

Multiple indium implant methods and devices and integrated circuits therefrom

Dual salicide process for optimum performance

Sub-critical-dimension integrated circuit features

Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity

Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices

Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps

Use of poly resistor implant to dope poly gates

High threshold NMOS source-drain formation with As, P and C to reduce damage

Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate

Transistor with improved source/drain extension dopant concentration

Transistor with bottomwall/sidewall junction capacitance reduction region and method

Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance

Controlled oxide growth over polysilicon gates for improved transistor characteristics

Fin-based laterally-diffused metal-oxide semiconductor field effect transistor

Activation of CMOS source/drain extensions by ultra-high temperature anneals

Raised source/drain transistor

Low leakage Schottky diode

Low leakage Schottky diode

Semiconductor device manufactured using a laminated stress layer

Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer

Method and system for forming a transistor having source and drain extensions

High mobility transistors

Multi-stage implant to improve device characteristics

Method for manufacturing an isolation structure using an energy beam treatment

Slim spacer implementation to improve drive current

NPN heterojunction bipolar transistor in CMOS flow

Epitaxial source/drain differential spacers

Hybrid high-k first and high-k last replacement gate process

High mobility transistors

Epitaxial source/drain differential spacers

Hybrid high-k first and high-k last replacement gate process

Transistor structure with silicided source and drain extensions and process for fabrication

Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance

High mobility transistors

Semiconductor structure that reduces the effects of gate cross diffusion and method of forming the structure

Semiconductor structure that reduces the effects of gate cross diffusion and method of forming the structure

Semiconductor device made by using a laser anneal to incorporate stress into a channel region

Low-voltage-Vt (CMOS) transistor design using a single mask and without any additional implants by way of tailoring the effective channel length (Leff)

Versatile system for forming uniform wafer surfaces

High mobility transistors

High mobility transistors

NPN heterojunction bipolar transistor in CMOS flow

MEHROTRA MANOJ

PMOS SiGe-last integration process

Transistor structure with silicided source and drain extensions and process for fabrication

Trench with reduced silicon loss

UNIV NORTH CAROLINA STATE

Schottky barrier rectifier with MOS trench

Bidirectional AC switching device with MOS-gated turn-on and turn-off control

QUALCOMM INC

Systems and methods for adaptive clock design

Adjust voltage for thermal mitigation

NIIMI HIROAKI

Formation of nitrogen containing dielectric layers having an improved nitrogen distribution