Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity

Abstract

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer ( 210 ) over a transistor device having source/drain regions ( 150, 155 ) located over a substrate ( 110 ), the capping layer ( 210 ) having a degree of reflectivity, and annealing the transistor device through the capping layer ( 210 ) using photons ( 310 ), the annealing of the transistor device affected by the degree of reflectivity.

1. A method for manufacturing a semiconductor device, comprising:
 forming a capping layer over a first transistor device having source/drain regions located over a substrate, the capping layer having a degree of reflectivity; 
 annealing the first transistor device through the capping layer using photons, the annealing of the first transistor device affected by the degree of reflectivity such that during the anneal, an anneal temperature at the first transistor device is different that an anneal temperature at a second transistor device located on the substrate. 
 
   
   
     2. The method as recited in  claim 1  wherein annealing the transistor device through the capping layer includes annealing the transistor device through a lattice structure of the capping layer and not through an opening in the capping layer. 
   
   
     3. The method as recited in  claim 1  wherein the degree of reflectivity governs a temperature of the anneal. 
   
   
     4. The method as recited in  claim 3  wherein a higher degree of reflectivity causes the temperature of the anneal to be lower and a lower degree of reflectivity causes the temperature of the anneal to be higher. 
   
   
     5. The method as recited in  claim 1  wherein forming the capping layer includes forming the capping layer over the first transistor device and the second transistor device, a portion of the capping layer located over the first transistor device having the degree of reflectivity and a portion of the capping layer located over the second transistor device having a different degree of reflectivity. 
   
   
     6. The method as recited in  claim 5  wherein the degree of reflectivity and the different degree of reflectivity are substantially controlled by a thickness of the capping layer located over the first transistor device and a thickness of the capping layer located over the second transistor device, respectively. 
   
   
     7. The method as recited in  claim 6  wherein the thickness of the capping layer located over the first transistor device is greater than the thickness of the capping layer located over the second transistor device, thereby causing the degree of reflectivity to be greater than the different degree of reflectivity. 
   
   
     8. The method as recited in  claim 7  wherein the degree of reflectivity and the different degree of reflectivity cause a temperature of the anneal of the first transistor device to be lower than a temperature of the anneal of the second transistor device. 
   
   
     9. The method as recited in  claim 5  wherein the degree of reflectivity and the different degree of reflectivity are substantially controlled by a material composition of the capping layer located over the first transistor device and a material composition of the capping layer located over the second transistor device. 
   
   
     10. The method as recited in  claim 9  wherein the material composition of the capping layer located over the first transistor device and the material composition of the capping layer located over the second transistor device causes the degree of reflectivity to be greater than the different degree of reflectivity. 
   
   
     11. The method as recited in  claim 10  wherein the degree of reflectivity and the different degree of reflectivity cause a temperature of the anneal of the first transistor device to be lower than a temperature of the anneal of the second transistor device. 
   
   
     12. The method as recited in  claim 1  wherein the capping layer is not located over the second transistor device, the degree of reflectivity of the capping layer causing a temperature of the anneal of the first transistor device to be lower than a temperature of the anneal of the second transistor device. 
   
   
     13. The method as recited in  claim 1  wherein annealing the transistor device through the capping layer using photons includes annealing the transistor device through the capping layer using a monochromatic energy source. 
   
   
     14. A method for manufacturing an integrated circuit, comprising:
 forming at least first and second transistor devices over a substrate, each of the first and second transistor devices having source/drain regions in the substrate; 
 forming a capping layer over at least the first transistor device, the capping layer having a degree of reflectivity; 
 annealing the first and second transistor devices using photons, the degree of reflectivity of the capping layer causing an annealing temperature of the first transistor device to be lower than an annealing temperature of the second transistor device; and 
 forming interconnects within dielectric layers located over the first and second transistor devices to form an operational integrated circuit. 
 
   
   
     15. The method as recited in  claim 14  wherein annealing the first transistor device through the capping layer includes annealing the first transistor device through a lattice structure of the capping layer and not through an opening in the capping layer. 
   
   
     16. The method as recited in  claim 14  wherein a higher degree of reflectivity causes the annealing temperature of the first transistor device to be lower and a lower degree of reflectivity causes the annealing temperature of the first transistor device to be higher. 
   
   
     17. The method as recited in  claim 14  wherein forming the capping layer includes forming the capping layer over at least the first transistor device and the second transistor device, a portion of the capping layer located over the first transistor device having the degree of reflectivity and a portion of the capping layer located over the second transistor device having a different degree of reflectivity. 
   
   
     18. The method as recited in  claim 17  wherein the degree of reflectivity and the different degree of reflectivity are substantially controlled by a thickness of the capping layer located over the first transistor device and a thickness of the capping layer located over the second transistor device, respectively. 
   
   
     19. The method as recited in  claim 18  wherein the thickness of the capping layer located over the first transistor device is greater than the thickness of the capping layer located over the second transistor device, thereby causing the degree of reflectivity to be greater than the different degree of reflectivity. 
   
   
     20. The method as recited in  claim 17  wherein the degree of reflectivity and the different degree of reflectivity are substantially controlled by a material composition of the capping layer located over the first transistor device and a material composition of the capping layer located over the second transistor device. 
   
   
     21. The method as recited in  claim 20  wherein the material composition of the capping layer located over the first transistor device and the material composition of the capping layer located over the second transistor device causes the degree of reflectivity to be greater than the different degree of reflectivity. 
   
   
     22. The method as recited in  claim 14  wherein the capping layer is not located over the second transistor device, the degree of reflectivity of the capping layer causing the annealing temperature of the first transistor device to be lower than the annealing temperature of the second transistor device. 
   
   
     23. The method as recited in  claim 14  wherein the first transistor device and the second transistor device are different types of devices. 
   
   
     24. The method as recited in  claim 14  wherein the first transistor device and the second transistor device are located at least about 100 μm apart.