Inventor

JAIN AMITABH

IN71 patents

⚠️ This page may combine multiple inventors who share the name “JAIN AMITABH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAIN AMITABH

TEXAS INSTRUMENTS INC

Source/drain extensions having highly activated and extremely abrupt junctions

Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors

Complementary junction-narrowing implants for ultra-shallow junctions

Methods and apparatus for improved mosfet drain extension activation

System for reducing segregation and diffusion of halo implants into highly doped regions

Nickel alloy silicide including indium and a method of manufacture therefor

Nickel alloy silicide including indium and a method of manufacture therefor

Nickel silicide including indium and a method of manufacture therefor

Nickel silicide including indium and a method of manufacture therefor

Source drain and extension dopant concentration

ZTCR poly resistor in replacement gate flow

CMOS fabrication process

Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity

Solid phase epitaxy recrystallization by laser annealing

Implantation of carbon and/or fluorine in NMOS fabrication

Gate edge diode leakage reduction

Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate

Use of indium to define work function of p-type doped polysilicon

Transistor with improved source/drain extension dopant concentration

Complementary junction-narrowing implants for ultra-shallow junctions

Reduced hydrogen sidewall spacer oxide

Drain induced barrier lowering with anti-punch-through implant

Ultra-shallow arsenic junction formation in silicon germanium

Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length

Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit

Methodology of improving the manufacturability of laser anneal

Method for forming strained channel PMOS devices and integrated circuits therefrom

Antimony ion implantation for semiconductor components

Method of forming amorphous source/drain extensions

Activation of CMOS source/drain extensions by ultra-high temperature anneals

Method for preparing a source material including forming a paste for ion implantation

Method and system for improved nickel silicide

Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor

Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same

Source/drain extension fabrication process with direct implantation

Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates

Integrated circuit having chemically modified spacer surface

ICERTIS INC

Risk prediction based on automated analysis of documents

Clause discovery for validation of documents

Clause discovery for validation of documents

Automated training and selection of models for document analysis

Risk prediction based on automated analysis of documents

Automated training and selection of models for document analysis

Representing documents using document keys

Representing documents using document keys

NANDAKUMAR MAHALINGAM

Indium, carbon and halogen doping for PMOS transistors

CMOS fabrication process

Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit

JAIN AMITABH

Strain-engineered MOSFETs having rimmed source-drain recesses

SONG SEUNG-CHUL

Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor