Source drain and extension dopant concentration

Abstract

A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

What is claimed is:  
     
       1. A method of forming a semiconductor device, comprising: 
       forming a gate stack on a semiconductor surface wherein said gate stack comprises vertical sides;  
       forming one or more sidewall spacer layers on said vertical sides of said gate stack;  
       doping at least one region in said semiconductor surface adjacent to said sidewall spacers;  
       forming first and second sidewall bodies on opposing sides of the gate stack, wherein the formation of the first and second sidewall bodies comprises:  
       forming a first sidewall-forming layer outwardly from said sidewall spacer layers;  
       exposing the semiconductor device to a heating cycle in a single wafer reactor; and  
       forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer, the formation of the second sidewall-forming layer occurring in an environment comprising bistertiarybutylamino-silane (BTBAS) that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.  
     
     
       2. The method of  claim 1 , wherein the at least one of the one or more sidewall spacer layers comprises a dielectric material selected from a group consisting of nitride, oxide, oxi-nitride, and silicon dioxide. 
     
     
       3. The method of  claim 1 , wherein the at least one region of the partially formed semiconductor device comprises an extension region. 
     
     
       4. The method of  claim 1 , wherein the first sidewall-forming layer comprises dielectric material selected from a group consisting of oxide, oxi-nitride, or silicon dioxide. 
     
     
       5. The method of  claim 4 , wherein the semiconductor device is placed in the single wafer reactor for approximately one to two minutes. 
     
     
       6. The method of  claim 1 , wherein the temperature in the single wafer reactor is approximately 600 to 700° C. 
     
     
       7. The method of  claim 4 , wherein the semiconductor device is placed in a batch furnace at a reduced deposition temperature on the order of 500 to 600° C. 
     
     
       8. The method of  claim 1 , wherein the second sidewall-forming layer comprises a dielectric material selected from a group consisting of oxi-nitride or nitride. 
     
     
       9. The method of  claim 1 , wherein forming the second sidewall spacer layer comprises introducing carbon impurities of a concentration on the order of 3 to 15 percent. 
     
     
       10. The method of  claim 1 , wherein the semiconductor device comprises a transistor. 
     
     
       11. The method of  claim 1 , further comprising implanting first and second source drain regions into the substrate, the first and second source drain regions self-aligned relative to an outward surface of the first and second sidewall bodies. 
     
     
       12. The method of  claim 1 , further comprising forming first and second sidewall spacers on opposing sides of the gate stack, the first and second sidewall spacers formed before forming first and second source drain extension regions, the first and second source drain extension regions self-aligned relative to an outward surface of the first and second sidewall spacers, respectively.