Inventor

BU HAOWEN

US73 patents

⚠️ This page may combine multiple inventors who share the name “BU HAOWEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BU HAOWEN

TEXAS INSTRUMENTS INC

Forming a retrograde well in a transistor to enhance performance of the transistor

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Method for fabricating transistor gate structures and gate dielectrics thereof

Increased drive current by isotropic recess etch

Sidewall processes using alkylsilane precursors for MOS transistor fabrication

Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors

Systems and methods that selectively modify liner induced stress

PMD liner nitride films and fabrication methods for improved NMOS performance

Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Methods, systems and structures for forming improved transistors

Transistor fabrication methods using reduced width sidewall spacers

Method for integrating high-k dielectrics in transistor devices

Source drain and extension dopant concentration

Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Method for fabricating dual work function metal gates

Transistor fabrication methods using dual sidewall spacers

Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation

Drive current improvement from recessed SiGe incorporation close to gate

Semiconductor device having a fully silicided gate electrode and method of manufacture therefor

Process to enable ferroelectric layers on large area substrates

Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige

System and method for mitigating oxide growth in a gate dielectric

Forming a retrograde well in a transistor to enhance performance of the transistor

System and method for mitigating oxide growth in a gate dielectric

Transistor with improved source/drain extension dopant concentration

Precision capacitor

Reduced hydrogen sidewall spacer oxide

IC with 3D metal-insulator-metal capacitor

Capacitor with improved voltage coefficients

Multi-step deposition of ferroelectric dielectric material

Methodology of improving the manufacturability of laser anneal

Antimony ion implantation for semiconductor components

Nitrogen based implants for defect reduction in strained silicon

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

CMOS transistor using high stress liner layer

Method of incorporating stress into a transistor channel by use of a backside layer

High performance CMOS transistors using PMD liner stress

Integration scheme to build resistor, capacitor, efuse using silicon-rich dielectric layer as a base dielectric

Precision capacitor

Precision capacitor

Precision capacitor

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Method of manufacturing gate sidewalls that avoids recessing

Interface improvement by stress application during oxide growth through use of backside films

Method for forming a metal silicide

Shallow trench isolation structure with nitride pullback by implantation treatment

BEVAN MALCOLM J

System and method for mitigating oxide growth in a gate dielectric

BU HAOWEN

Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

CHAKRAVARTHI SRINIVASAN

Nitrogen based implants for defect reduction in strained silicon