Inventor

NANDAKUMAR MAHALINGAM

US91 patents

⚠️ This page may combine multiple inventors who share the name “NANDAKUMAR MAHALINGAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NANDAKUMAR MAHALINGAM

TEXAS INSTRUMENTS INC

Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness

Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing

Semiconductor devices with pocket implant and counter doping

Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing

Use of a thin nitride spacer in a split gate embedded analog process

Semiconductor devices with pocket implant and counter doping

Transistor having ultrashallow source and drain junctions with reduced gate overlap and method

Dual-counterdoped channel field effect transistor and method

Channel implant for improving NMOS ESD robustness

Integrated circuit isolation

Combination test structures for in-situ measurements during fabrication of semiconductor devices

ZTCR poly resistor in replacement gate flow

Dual NSD implants for reduced Rsd in an NMOS transistor

CMOS fabrication process

Disposable sidewall spacer process for integrated circuits

Mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps

Shallow trench isolation with conductive hard mask for in-line moat/trench width electrical measurements

Implantation of carbon and/or fluorine in NMOS fabrication

Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment

Compensated well ESD diodes with reduced capacitance

Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask

Method of making multiple threshold voltage integrated of circuit transistors

Fringe capacitance reduction for replacement gate CMOS

Method of pocket implant modeling for a CMOS process

Conductive spline for metal gates

Semiconductor device with low noise transistor and low temperature coefficient resistor

Dummy contacts to mitigate plasma charging damage to gate dielectrics

Compensated well ESD diodes with reduced capacitance

Pocket counterdoping for gate-edge diode leakage reduction

Polysilicon resistor implant for reduced resistance temperature coefficient variability

Channel stop and well dopant migration control implant for reduced MOS threshold voltage mismatch

Advanced poly resistor and CMOS transistor

High resistance poly resistor

Channel stop and well dopant migration control implant for reduced MOS threshold voltage mismatch

High resistance poly resistor

Gate implant for reduced resistance temperature coefficient variability

Fringe capacitance reduction for replacement gate CMOS

Combining ZTCR resistor with laser anneal for high performance PMOS transistor

Transistor with deep Nwell implanted through the gate

Flatband shift for improved transistor performance

Carbon and nitrogen doping for selected PMOS transistors on an integrated circuit

Transistor with reduced short channel effects and method

Method of incorporating stress into a transistor channel by use of a backside layer

Transistor with reduced short channel effects and method

Integration scheme to build resistor, capacitor, efuse using silicon-rich dielectric layer as a base dielectric

UNIV NORTH CAROLINA STATE

Unit cell arrangement for emitter switched thyristor with base resistance control

Integrated multicelled semiconductor switching device for high current applications

NANDAKUMAR MAHALINGAM

Indium, carbon and halogen doping for PMOS transistors

CMOS fabrication process

TEXAS INSTR INCORPATED

Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride