Transistor with reduced short channel effects and method

Abstract

A method of fabricating a transistor ( 10 ) comprises forming source and drain regions ( 46 ) and ( 47 ) using a first sidewall ( 42 ) and ( 43 ) as a mask and forming a deep blanket source and drain regions ( 54 ) and ( 56 ) using a second sidewall ( 50 ) and ( 51 ) as a mask, the second sidewall ( 50 ) and ( 51 ) comprising at least part of the first sidewall ( 42 ) and ( 43 ).

1. A CMOS device, comprising:
 a semiconductor substrate having a surface;  
 an nMOS transistor near the surface of the substrate having a first gate element over the semiconductor substrate, a first channel region near the first gate element, and an n-type source region having a first n-type dopant profile, a second n-type dopant file, and a third n-type dopant profile, the third n-type dopant receding from the first channel region; and  
 a pMOS transistor near the surface of the substrate having a second gate element over the semiconductor substrate, a second channel region near the second gate element and a p-type source region having the third n-type dopant profile, the third n-type dopant profile receding from the second channel region.  
 
   
   
     2. The CMOS device of  claim 1 , wherein the first n-type dopant profile is a source extension ion implant profile, the second n-type dopant profile is a shallow source body ion implant profile, and the third n-type dopant profile is a blanket ion implant profile. 
   
   
     3. The CMOS device of  claim 1 , wherein the nMOS transistor further comprises a first gate edge nearer the second n-type dopant profile than the third n-type dopant profile. 
   
   
     4. The CMOS device of  claim 3 , wherein a two-layered sidewall is affixed to the first gate edge. 
   
   
     5. The CMOS device of  claim 3 , wherein a single-layered sidewall is affixed to the first gate edge. 
   
   
     6. A CMOS device, comprising:
 a semiconductor substrate having a surface;  
 a pMOS transistor near the surface of the substrate having a first gate element over the semiconductor substrate, a first channel region near the first gate element, and a p-type source region having a first p-type dopant profile, a second p-type dopant file, and a third p-type dopant profile, the third p-type dopant receding from the first channel region; and  
 an nMOS transistor near the surface of the substrate having a second gate element over the semiconductor substrate, a second channel region near the second gate element and an n-type source region having the third p-type dopant profile, the third p-type dopant profile receding from the second channel region.  
 
   
   
     7. The CMOS device of  claim 6 , wherein the first p-type dopant profile is a source extension ion implant profile, the second p-type dopant profile is a shallow source body ion implant profile, and the third p-type dopant profile is a blanket ion implant profile. 
   
   
     8. The CMOS device of  claim 6 , wherein the pMOS transistor further comprises a first gate edge nearer the second p-type dopant profile than the third p-type dopant profile. 
   
   
     9. The CMOS device of  claim 8 , wherein a two-layered sidewall is affixed to the first gate edge. 
   
   
     10. The CMOS device of  claim 8 , wherein a single-layered sidewall is affixed to the first gate edge.