Inventor
CHANG CHEANG-WHANG
US21 patents
⚠️ This page may combine multiple inventors who share the name “CHANG CHEANG-WHANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
20 patentsUS10770430B1Sep 8, 2020
Package integration for memory devices
XILINX INC53 citations97
US10692837B1Jun 23, 2020
Chip package assembly with modular core dice
XILINX INC35 citations93
US10262911B1Apr 16, 2019
Circuit for and method of testing bond connections between a first die and a second die
XILINX INC51 citations92
US11054461B1Jul 6, 2021
Test circuits for testing a die stack
XILINX INC12 citations84
US10431565B1Oct 1, 2019
Wafer edge partial die engineered for stacked die yield
XILINX INC10 citations84
US9412674B1Aug 9, 2016
Shielded wire arrangement for die testing
XILINX INC12 citations83
US11901338B2Feb 13, 2024
Interwafer connection structure for coupling wafers in a wafer stack
XILINX INC2 citations73
US11488936B2Nov 1, 2022
Stacked silicon package assembly having vertical thermal management
XILINX INC2 citations73
US11205639B2Dec 21, 2021
Integrated circuit device with stacked dies having mirrored circuitry
XILINX INC2 citations73
US11145566B2Oct 12, 2021
Stacked silicon package assembly having thermal management
XILINX INC5 citations73
US11585854B1Feb 21, 2023
Runtime measurement of process variations and supply voltage characteristics
XILINX INC6 citations71
US12557660B2Feb 17, 2026
Integrated circuit (IC) protections comprising electromagnetic radiation blocking material
XILINX INC0 citations62
US12068257B1Aug 20, 2024
Integrated circuit (IC) structure protection scheme
XILINX INC0 citations62
US11355412B2Jun 7, 2022
Stacked silicon package assembly having thermal management
XILINX INC1 citations62
US11114344B1Sep 7, 2021
IC die with dummy structures
XILINX INC1 citations62
US8810269B2Aug 19, 2014
Method of testing a semiconductor structure
XILINX INC3 citations60
US12045469B2Jul 23, 2024
Single event upset tolerant memory device
XILINX INC0 citations51
US10096502B2Oct 9, 2018
Method and apparatus for assembling and testing a multi-integrated circuit package
XILINX INC0 citations51
US10103139B2Oct 16, 2018
Method and design of low sheet resistance MEOL resistors
XILINX INC0 citations41
US10379155B2Aug 13, 2019
In-die transistor characterization in an IC
XILINX INC0 citations37