Stacked silicon package assembly having thermal management

Abstract

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

What is claimed is: 
     
       1. A chip package assembly comprising:
 a substrate; 
 a first integrated circuit (IC) die mounted to the substrate; 
 a cover disposed over the first IC die; and 
 a plurality of extra-die conductive posts disposed between the cover and substrate, the plurality of extra-die conductive posts providing a heat transfer path between the cover and the substrate that is laterally outward of the first IC die, wherein the plurality of extra-die conductive posts further comprises:
 a seed layer disposed on the substrate; and 
 a bulk thermally conductive layer disposed on the seed layer. 
 
 
     
     
       2. The chip package assembly of  claim 1  further comprising:
 a dielectric filler disposed between the substrate and the cover disposed over the first IC die, the dielectric filler having a plurality of holes in which the plurality of extra-die conductive posts are disposed. 
 
     
     
       3. The chip package assembly of  claim 2 , wherein a first conductive post of the plurality of extra-die conductive posts further comprises:
 a heat pipe having a first end exposed through a first hole of the plurality of holes and in conductive thermal contact with the cover, the heat pipe having a second end exposed through the first hole and in conductive thermal contact with the substrate. 
 
     
     
       4. The chip package assembly of  claim 3  wherein the heat pipe comprises a phase changing material in a sealed cavity of the heat pipe. 
     
     
       5. The chip package assembly of  claim 1  further comprising:
 a second IC die mounted to the substrate, the second IC die configured as a memory die and the first IC die configured as a logic die. 
 
     
     
       6. The chip package assembly of  claim 5  further comprising:
 a stiffener bonded to the substrate and circumscribing the first and second IC dies. 
 
     
     
       7. The chip package assembly of  claim 6 , wherein at least a first conductive post of the plurality of extra-die conductive posts is disposed between one of the first and second IC dies and the stiffener. 
     
     
       8. The chip package assembly of  claim 7 , wherein at least a second conductive post of the plurality of extra-die conductive posts is disposed between the first and second IC dies. 
     
     
       9. The chip package assembly of  claim 1 , wherein a first conductive post of the plurality of extra-die conductive posts comprises a thermally conductive material selected from a group consisting of solder paste, metal fibers, metal powder, metal particles, metal balls, and thermally conductive adhesive. 
     
     
       10. A high bandwidth memory chip package assembly comprising:
 a substrate; 
 at least a first memory die mounted to the substrate; 
 at least a first logic die mounted to and communicatively coupled to the substrate; 
 a cover disposed over the first memory die and the first logic die; 
 a dielectric filler disposed around the first memory die and the first logic die, the dielectric filler disposed between the substrate and the cover, the dielectric filler having at least one hole; and 
 a first conductive post disposed in the hole in the dielectric filler and providing a heat transfer path between the cover and substrate, wherein the plurality of extra-die conductive posts further comprises:
 a seed layer disposed on the substrate; and 
 a bulk thermally conductive layer disposed on the seed layer. 
 
 
     
     
       11. The high bandwidth memory chip package assembly of  claim 10  further comprising:
 a stiffener bonded to the substrate and circumscribing the first memory die and the first logic die. 
 
     
     
       12. The high bandwidth memory chip package assembly of  claim 11 , wherein the first conductive post is disposed between the first memory die and the first logic die. 
     
     
       13. The high bandwidth memory chip package assembly of  claim 11 , wherein the first conductive post is disposed between (1) the first memory die and the first logic die and (2) the stiffener. 
     
     
       14. The high bandwidth memory chip package assembly of  claim 10 , wherein the first conductive post further comprises:
 a heat pipe having a first end exposed through the at least one hole and in conductive thermal contact with the cover, the heat pipe having a second end exposed through the at least one hole and in conductive thermal contact with the substrate. 
 
     
     
       15. The high bandwidth memory chip package assembly of  claim 14  wherein the heat pipe comprises a phase changing material in a sealed cavity of the heat pipe. 
     
     
       16. The high bandwidth memory chip package assembly of  claim 10 , wherein the first conductive post comprises a thermally conductive material comprised of powder, metal wool, or discrete shapes. 
     
     
       17. A chip package assembly comprising:
 a substrate; 
 a first integrated circuit (IC) die mounted to the substrate; 
 a cover disposed over the first IC die; 
 a dielectric filler disposed between the substrate and the cover; and 
 a plurality of extra-die conductive material disposed in and extending from the substrate through the dielectric filler, wherein the plurality of extra-die conductive posts further comprises:
 a seed layer disposed on the substrate; and 
 a bulk thermally conductive layer disposed on the seed layer. 
 
 
     
     
       18. The chip package assembly of  claim 17 , wherein each of the plurality of extra-die conductive material comprises at least one of powder, metal wool, discrete shapes, solder paste, metal fibers, metal powder, metal particles, metal balls, and thermally conductive adhesive.