Inventor · disambiguated record
Henley Liu
Also filed as: LIU HENLEY
22 granted patents·3 pending applications·274 citations·filing 2010–2024
95Inventor score
Top patents by PatentIndex Score
25 records- 0198US10770430B1Package integration for memory devicesXILINX INC·Filed 2019·Granted Sep 8, 2020·53 cites·20 claims
- 0297US10692837B1Chip package assembly with modular core diceXILINX INC·Filed 2018·Granted Jun 23, 2020·35 cites·18 claims
- 0396US10529645B2Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal managementXILINX INC·Filed 2017·Granted Jan 7, 2020·26 cites·20 claims
- 0496US10262911B1Circuit for and method of testing bond connections between a first die and a second dieXILINX INC·Filed 2016·Granted Apr 16, 2019·51 cites·20 claims
- 0594US9337138B1Capacitors within an interposer coupled to supply and ground planes of a substrateABUGHARBIEH KHALDOON S·Filed 2012·Granted May 10, 2016·36 cites·16 claims
- 0693US11054461B1Test circuits for testing a die stackXILINX INC·Filed 2019·Granted Jul 6, 2021·12 cites·18 claims
- 0792US11901338B2Interwafer connection structure for coupling wafers in a wafer stackXILINX INC·Filed 2021·Granted Feb 13, 2024·2 cites·19 claims
- 0892US10431565B1Wafer edge partial die engineered for stacked die yieldXILINX INC·Filed 2018·Granted Oct 1, 2019·10 cites·11 claims
- 0989US9412674B1Shielded wire arrangement for die testingXILINX INC·Filed 2013·Granted Aug 9, 2016·12 cites·20 claims
- 1089US8354671B1Integrated circuit with adaptive VGG settingXILINX INC·Filed 2010·Granted Jan 15, 2013·11 cites·15 claims
- 1188US10720377B2Electronic device apparatus with multiple thermally conductive paths for heat dissipationXILINX INC·Filed 2018·Granted Jul 21, 2020·6 cites·20 claims
- 1285US11205639B2Integrated circuit device with stacked dies having mirrored circuitryXILINX INC·Filed 2020·Granted Dec 21, 2021·2 cites·20 claims
- 1385US10629512B2Integrated circuit die with in-chip heat sinkXILINX INC·Filed 2018·Granted Apr 21, 2020·4 cites·20 claims
- 1485US8802454B1Methods of manufacturing a semiconductor structureRAHMAN ARIFUR·Filed 2011·Granted Aug 12, 2014·7 cites·20 claims
- 1580US11114344B1IC die with dummy structuresXILINX INC·Filed 2020·Granted Sep 7, 2021·1 cites·20 claims
- 1675US10319606B1Chip package assembly with enhanced interconnects and method for fabricating the sameXILINX INC·Filed 2017·Granted Jun 11, 2019·2 cites·20 claims
- 1770US8810269B2Method of testing a semiconductor structureXILINX INC·Filed 2012·Granted Aug 19, 2014·3 cites·19 claims
- 1869US11355412B2Stacked silicon package assembly having thermal managementXILINX INC·Filed 2018·Granted Jun 7, 2022·1 cites·18 claims
- 1962US2025149390A1Wafer process for probing bump placement on multiple small power pads without displacing surrounding signal padsXILINX INC·Filed 2024·Application pending·0 cites
- 2057US10527670B2Testing system for lid-less integrated circuit packagesXILINX INC·Filed 2017·Granted Jan 7, 2020·0 cites·20 claims
- 2155US2024321793A1Chip package assembly with enhanced solder pitchXILINX INC·Filed 2023·Application pending·0 cites
- 2254US12068257B1Integrated circuit (IC) structure protection schemeXILINX INC·Filed 2020·Granted Aug 20, 2024·0 cites·15 claims
- 2353US2024038556A1Method for mitigating warpage on stacked wafersXILINX INC·Filed 2022·Application pending·0 cites
- 2447US10971474B1Package integration for high bandwidth memoryXILINX INC·Filed 2019·Granted Apr 6, 2021·0 cites·20 claims
- 2545US10593638B2Methods of interconnect for high density 2.5D and 3D integrationXILINX INC·Filed 2017·Granted Mar 17, 2020·0 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →