Inventor · disambiguated record
Myongseob Kim
Also filed as: KIM MYONGSEOB
20 granted patents·2 pending applications·332 citations·filing 2007–2023
95Inventor score
Files withXILINX INC18AHN JAE-GYUNG1CORNELL RES FOUNDATION INC1LAKSHMINARAYANAN SETHURAMAN1RAHMAN ARIFUR1
Top patents by PatentIndex Score
22 records- 0198US10770430B1Package integration for memory devicesXILINX INC·Filed 2019·Granted Sep 8, 2020·53 cites·20 claims
- 0297US10692837B1Chip package assembly with modular core diceXILINX INC·Filed 2018·Granted Jun 23, 2020·35 cites·18 claims
- 0396US10529645B2Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal managementXILINX INC·Filed 2017·Granted Jan 7, 2020·26 cites·20 claims
- 0496US10262911B1Circuit for and method of testing bond connections between a first die and a second dieXILINX INC·Filed 2016·Granted Apr 16, 2019·51 cites·20 claims
- 0594US7960776B2Transistor with floating gate and electretCORNELL RES FOUNDATION INC·Filed 2007·Granted Jun 14, 2011·86 cites·11 claims
- 0693US11054461B1Test circuits for testing a die stackXILINX INC·Filed 2019·Granted Jul 6, 2021·12 cites·18 claims
- 0792US11901338B2Interwafer connection structure for coupling wafers in a wafer stackXILINX INC·Filed 2021·Granted Feb 13, 2024·2 cites·19 claims
- 0892US10431565B1Wafer edge partial die engineered for stacked die yieldXILINX INC·Filed 2018·Granted Oct 1, 2019·10 cites·11 claims
- 0989US9412674B1Shielded wire arrangement for die testingXILINX INC·Filed 2013·Granted Aug 9, 2016·12 cites·20 claims
- 1089US8987009B1Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) productXILINX INC·Filed 2013·Granted Mar 24, 2015·8 cites·12 claims
- 1185US11205639B2Integrated circuit device with stacked dies having mirrored circuitryXILINX INC·Filed 2020·Granted Dec 21, 2021·2 cites·20 claims
- 1285US8802454B1Methods of manufacturing a semiconductor structureRAHMAN ARIFUR·Filed 2011·Granted Aug 12, 2014·7 cites·20 claims
- 1381US8542514B1Memory structure having SRAM cells and SONOS devicesLAKSHMINARAYANAN SETHURAMAN·Filed 2008·Granted Sep 24, 2013·20 cites·10 claims
- 1480US11114344B1IC die with dummy structuresXILINX INC·Filed 2020·Granted Sep 7, 2021·1 cites·20 claims
- 1570US8810269B2Method of testing a semiconductor structureXILINX INC·Filed 2012·Granted Aug 19, 2014·3 cites·19 claims
- 1669US11355412B2Stacked silicon package assembly having thermal managementXILINX INC·Filed 2018·Granted Jun 7, 2022·1 cites·18 claims
- 1767US9236367B1Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) productXILINX INC·Filed 2015·Granted Jan 12, 2016·1 cites·17 claims
- 1858US8329568B1Semiconductor device and method for making the sameAHN JAE-GYUNG·Filed 2010·Granted Dec 11, 2012·2 cites·20 claims
- 1955US2024321793A1Chip package assembly with enhanced solder pitchXILINX INC·Filed 2023·Application pending·0 cites
- 2054US12068257B1Integrated circuit (IC) structure protection schemeXILINX INC·Filed 2020·Granted Aug 20, 2024·0 cites·15 claims
- 2154US11114360B1Multi-die device structures and methodsXILINX INC·Filed 2019·Granted Sep 7, 2021·0 cites·20 claims
- 2253US2024038556A1Method for mitigating warpage on stacked wafersXILINX INC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →