Inventor · disambiguated record
Cheang-Whang Chang
Also filed as: CHANG CHEANG-WHANG
20 granted patents·2 pending applications·202 citations·filing 2011–2023
94Inventor score
Top patents by PatentIndex Score
22 records- 0198US10770430B1Package integration for memory devicesXILINX INC·Filed 2019·Granted Sep 8, 2020·53 cites·20 claims
- 0297US11145566B2Stacked silicon package assembly having thermal managementXILINX INC·Filed 2020·Granted Oct 12, 2021·5 cites·20 claims
- 0397US10692837B1Chip package assembly with modular core diceXILINX INC·Filed 2018·Granted Jun 23, 2020·35 cites·18 claims
- 0496US10262911B1Circuit for and method of testing bond connections between a first die and a second dieXILINX INC·Filed 2016·Granted Apr 16, 2019·51 cites·20 claims
- 0593US11054461B1Test circuits for testing a die stackXILINX INC·Filed 2019·Granted Jul 6, 2021·12 cites·18 claims
- 0692US11901338B2Interwafer connection structure for coupling wafers in a wafer stackXILINX INC·Filed 2021·Granted Feb 13, 2024·2 cites·19 claims
- 0792US10431565B1Wafer edge partial die engineered for stacked die yieldXILINX INC·Filed 2018·Granted Oct 1, 2019·10 cites·11 claims
- 0889US9412674B1Shielded wire arrangement for die testingXILINX INC·Filed 2013·Granted Aug 9, 2016·12 cites·20 claims
- 0986US11585854B1Runtime measurement of process variations and supply voltage characteristicsXILINX INC·Filed 2018·Granted Feb 21, 2023·6 cites·19 claims
- 1085US11205639B2Integrated circuit device with stacked dies having mirrored circuitryXILINX INC·Filed 2020·Granted Dec 21, 2021·2 cites·20 claims
- 1185US8802454B1Methods of manufacturing a semiconductor structureRAHMAN ARIFUR·Filed 2011·Granted Aug 12, 2014·7 cites·20 claims
- 1280US11114344B1IC die with dummy structuresXILINX INC·Filed 2020·Granted Sep 7, 2021·1 cites·20 claims
- 1378US11488936B2Stacked silicon package assembly having vertical thermal managementXILINX INC·Filed 2019·Granted Nov 1, 2022·2 cites·20 claims
- 1470US8810269B2Method of testing a semiconductor structureXILINX INC·Filed 2012·Granted Aug 19, 2014·3 cites·19 claims
- 1569US11355412B2Stacked silicon package assembly having thermal managementXILINX INC·Filed 2018·Granted Jun 7, 2022·1 cites·18 claims
- 1660US12045469B2Single event upset tolerant memory deviceXILINX INC·Filed 2022·Granted Jul 23, 2024·0 cites·20 claims
- 1755US2024321793A1Chip package assembly with enhanced solder pitchXILINX INC·Filed 2023·Application pending·0 cites
- 1854US12068257B1Integrated circuit (IC) structure protection schemeXILINX INC·Filed 2020·Granted Aug 20, 2024·0 cites·15 claims
- 1953US2024038556A1Method for mitigating warpage on stacked wafersXILINX INC·Filed 2022·Application pending·0 cites
- 2047US10379155B2In-die transistor characterization in an ICXILINX INC·Filed 2014·Granted Aug 13, 2019·0 cites·16 claims
- 2147US10096502B2Method and apparatus for assembling and testing a multi-integrated circuit packageXILINX INC·Filed 2016·Granted Oct 9, 2018·0 cites·16 claims
- 2241US10103139B2Method and design of low sheet resistance MEOL resistorsXILINX INC·Filed 2015·Granted Oct 16, 2018·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →