Inventor

TREMAINE ROBERT B

US60 patents

⚠️ This page may combine multiple inventors who share the name “TREMAINE ROBERT B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TREMAINE ROBERT B

IBM

Systems and methods for memory module power management

Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint

System and method for dynamically allocating associative resources

Computer memory compression abort and bypass mechanism when cache write back buffer is full

Programmable logic circuit using three-dimensional stacking techniques

Systems and methods for providing remote pre-fetch buffers

Systems and methods for providing distributed technology independent memory controllers

Systems and methods for providing data modification operations in memory subsystems

Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables

System and method for using a compressed main memory based on degree of compressibility

System and method for providing DRAM device-level repair via address remappings external to the device

System, method and storage medium for providing data caching and data compression in a memory subsystem

Prioritizing and locking removed and subsequently reloaded cache lines

Compressor system memory organization and method for low latency access to uncompressed memory regions

Operating system thread scheduling for optimal heat dissipation

Systems and methods for providing memory modules with multiple hub devices

Method for selecting memory busses according to physical memory organization information associated with virtual address translation tables

Systems and methods for providing distributed autonomous power management in a memory system

Very high speed page operations in indirect accessed memory systems

Providing indeterminate read data latency in a memory system

Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables

Functional built-in self test for a chip

System, method and storage medium for providing data caching and data compression in a memory subsystem

Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache

Memory systems for automated computing machinery

Very high speed page operations in indirect accessed memory systems

Soft error resilient FPGA

Selective recompression of a string compressed by a plurality of diverse lossless compression techniques

Data compression utilizing longest common subsequence template

Accessing additional memory space with multiple processors

Accessing additional memory space with multiple processors

COTEUS PAUL W

Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device

Providing frame start indication in a memory system having indeterminate read data latency

Method and system for providing identification tags in a memory system having indeterminate data response times

Method and system for providing frame start indication in a memory system having indeterminate read data latency

TREMAINE ROBERT B

Memory page management in a tiered memory system

Memory package utilizing at least two types of memories

Memory package utilizing at least two types of memories

Memory architecture with policy based data storage

CORDERO EDGAR R

Programmable logic circuit using three-dimensional stacking techniques

Implementing chip to chip calibration within a TSV stack

Requesting a memory space by a memory controller

AGARWAL KANAK B

Selective recompression of a string compressed by a plurality of diverse lossless compression techniques

Data compression utilizing longest common subsequence template

KRIEGER ORRAN Y

Prefetch engine based translation prefetching

Quality of service scheduling for simultaneous multi-threaded processors

DREPS DANIEL M

Strobe offset in bidirectional memory strobe configurations

Strobe offset in bidirectional memory strobe configurations

GAO YAOQING

Software solution for cooperative memory-side and processor-side data prefetching

SHEN XIAOWEI

System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory