Soft error resilient FPGA

Abstract

A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

What is claimed is: 
     
       1. A field programmable gate array (FPGA), comprising:
 configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having a soft error (SER) resilience greater than an SER resilience of the non-hardened portion; 
 wherein the hardened portion comprises half-hardened CRAM cells, comprising a first asymmetric transistor stack having a single pFET connected in series with a pair of nFETs, and a second asymmetric transistor stack cross-coupled to the first asymmetric transistor stack, the second asymmetric transistor stack having a pair of pFETs connected in series with a single nFET. 
 
     
     
       2. The FPGA of  claim 1 , wherein the hardened portion is static random access memory (SRAM) and the hardened portion includes interleaved SRAM error correction coding (ECC) bits. 
     
     
       3. The FPGA of  claim 2 , wherein the non-hardened portion is SRAM and does not include interleaved SRAM ECC bits. 
     
     
       4. The FPGA of  claim 1 , wherein the hardened portion comprises at least one SER tolerant device, and the non-hardened portion does not include an SER tolerant device. 
     
     
       5. The FPGA of  claim 4 , wherein the SER tolerant device includes at least one of embedded dynamic random access memory (EDRAM), flash memory, hardened latches, and fuses.