Inventor

MULLER K PAUL

US58 patents

⚠️ This page may combine multiple inventors who share the name “MULLER K PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MULLER K PAUL

IBM

Double gated transistor and method of fabrication

FinFET SRAM cell using low mobility plane for cell stability and method for forming

Finfet SRAM cell using low mobility plane for cell stability and method for forming

Double SOI device with recess etch and epitaxy

Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication

SOI transistor with polysilicon seed

Double gated transistor and method of fabrication

Double gated vertical transistor with different first and second gate materials

Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices

Methods for roughening and volume expansion of trench sidewalls to form high capacitance trench cell for high density dram applications

Cooling system control and servicing based on time-based variation of an operational variable

Method and apparatus for overlay measurement

Apparatus and method for hardening latches in SOI CMOS devices

OPC trimming for performance

Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication

Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator

Built-in testing of unused element on chip

Ground-plane device with back oxide topography

Lateral patterning

Sublithographic fuses using a phase shift mask

Method of producing sulithographic fuses using a phase shift mask

Authenticating features of virtual server system

End-to-end protection for shrouded virtual servers

Template matching for resilience and security characteristics of sub-component chip designs

Detecting and removing bias in subjective judging

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Alignment insensitive D-cache cell

Polysilicon doped transistor

Non-destructive method and device for measuring the depth of a buried interface

Built-in testing of unused element on chip

Error protection for integrated circuits

Placement of storage cells on an integrated circuit

Shared error protection for register banks

CMOS circuits including a passive element having a low end resistance

Bit flip aware latch placement

Pattern recognition for proactive treatment of non-contiguous growing defects

Soft error resilient FPGA

Apparatus and method for hardening latches in SOI CMOS devices

Preventing cavitation in high aspect ratio dielectric regions of semiconductor device

Authenticating features of virtual server system

End-to end protection for shrouded virtual servers

Computer system using partially functional processor core

SIEMENS AG

Formation of a bottle shaped trench

Spatially uniform gas supply and pump configuration for large wafer diameters

In-situ measurement method and apparatus for semiconductor processing

Method of end point detection using a sinusoidal interference signal for a wet etch process

CABRAL JR CYRIL

Alpha particle blocking wire structure and method fabricating same

HADDERMAN SCOTT J

Proactive cooling of chips using workload information and controls

KEARNEY DANIEL J

Cooling system control and servicing based on time-based variation of an operational variable

CANNON ETHAN H

In-line stacking of transistors for soft error rate hardening