Inventor

CULP JAMES A

US48 patents

⚠️ This page may combine multiple inventors who share the name “CULP JAMES A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CULP JAMES A

IBM

Physical design system and method

Halo-free non-rectifying contact on chip with halo source/drain diffusion

Electrically driven optical proximity correction

Method for verification of resolution enhancement techniques and optical proximity correction in lithography

Method and apparatus for lithographically printing tightly nested and isolated device features using multiple mask exposures

Selective local metal cap layer formation for improved electromigration behavior

Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks

Integrated circuit (IC) design method, system and program product

OPC trimming for performance

Multilayer OPC for design aware manufacturing

Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells

Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designs

Design verification

Integrated circuit with uniform polysilicon perimeter density, method and design structure

Halo-free non-rectifying contact on chip with halo source/drain diffusion

Selective local metal cap layer formation for improved electromigration behavior

Selective local metal cap layer formation for improved electromigration behavior

Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage

Methods and structures for enhancing perimeter-to-surface area homogeneity

Verifying mask layout printability using simulation with adjustable accuracy

Double exposure double resist layer process for forming gate patterns

Methods and system for analysis and management of parametric yield

IC chip design modeling using perimeter density to electrical characteristic correlation

Mask inspection process accounting for mask writer proximity correction

Methodology to improve turnaround for integrated circuit design using geometrical hierarchy

Circuit enhancement by multiplicate-layer-handling circuit simulation

Selective local metal cap layer formation for improved electromigration behavior

Method and system for comparing lithographic processing conditions and or data preparation processes

CULP JAMES A

Methods and system for analysis and management of parametric yield

System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss

Spacer linewidth control

Methods and system for analysis and management of parametric yield

Nitride etch for improved spacer uniformity

Characterization of long range variability

Leakage aware design post-processing

Automated sensitivity definition and calibration for design for manufacturing tools

GLOBALFOUNDRIES INC

Correcting for stress induced pattern shifts in semiconductor manufacturing

Net-voltage-aware optical proximity correction (OPC)

Semiconductor layout generation

Rule and process assumption co-optimization using feature-specific layout-based statistical analyses

COHN JOHN M

Physical design system and method

Physical design system and method

BANERJEE SHAYAK

Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance

Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance

MUKHERJEE MAHARAJ

Multilayer OPC for design aware manufacturing

Fast and accurate method to simulate intermediate range flare effects

MENTOR GRAPHICS CORP

Methods and system for analysis and management of parametric yield

BASHABOINA PAVAN Y

Yield enhancement by multiplicate-layer-handling optical correction